Search

Michael Thanh Tran

Examiner (ID: 2981, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818
Total Applications
3089
Issued Applications
2919
Pending Applications
108
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7003715 [patent_doc_number] => 20050169028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Content addressable memory cell architecture' [patent_app_type] => utility [patent_app_number] => 10/782388 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5451 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20050169028.pdf [firstpage_image] =>[orig_patent_app_number] => 10782388 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/782388
Content addressable memory cell architecture Feb 18, 2004 Issued
Array ( [id] => 7009498 [patent_doc_number] => 20050063214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/780590 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 32836 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20050063214.pdf [firstpage_image] =>[orig_patent_app_number] => 10780590 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/780590
Semiconductor integrated circuit device Feb 18, 2004 Abandoned
Array ( [id] => 1067395 [patent_doc_number] => 06847560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Method and circuit for generating constant slew rate output signal' [patent_app_type] => utility [patent_app_number] => 10/708232 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 7930 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/847/06847560.pdf [firstpage_image] =>[orig_patent_app_number] => 10708232 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708232
Method and circuit for generating constant slew rate output signal Feb 17, 2004 Issued
Array ( [id] => 7621663 [patent_doc_number] => 06977838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-20 [patent_title] => 'Method and system for providing a programmable current source for a magnetic memory' [patent_app_type] => utility [patent_app_number] => 10/781482 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8808 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977838.pdf [firstpage_image] =>[orig_patent_app_number] => 10781482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781482
Method and system for providing a programmable current source for a magnetic memory Feb 16, 2004 Issued
Array ( [id] => 939224 [patent_doc_number] => 06972998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Double data rate memory devices including clock domain alignment circuits and methods of operation thereof' [patent_app_type] => utility [patent_app_number] => 10/774904 [patent_app_country] => US [patent_app_date] => 2004-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972998.pdf [firstpage_image] =>[orig_patent_app_number] => 10774904 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/774904
Double data rate memory devices including clock domain alignment circuits and methods of operation thereof Feb 8, 2004 Issued
Array ( [id] => 568776 [patent_doc_number] => 07161833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Self-boosting system for flash memory cells' [patent_app_type] => utility [patent_app_number] => 10/774014 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 33 [patent_no_of_words] => 12289 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161833.pdf [firstpage_image] =>[orig_patent_app_number] => 10774014 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/774014
Self-boosting system for flash memory cells Feb 5, 2004 Issued
Array ( [id] => 6937706 [patent_doc_number] => 20050111267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/769192 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8791 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20050111267.pdf [firstpage_image] =>[orig_patent_app_number] => 10769192 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/769192
Semiconductor integrated circuit device Jan 28, 2004 Issued
Array ( [id] => 661138 [patent_doc_number] => 07106635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-12 [patent_title] => 'Bitline booster circuit and method' [patent_app_type] => utility [patent_app_number] => 10/769130 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4856 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/106/07106635.pdf [firstpage_image] =>[orig_patent_app_number] => 10769130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/769130
Bitline booster circuit and method Jan 28, 2004 Issued
Array ( [id] => 973932 [patent_doc_number] => 06937511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Circuit and method for programming charge storage memory cells' [patent_app_type] => utility [patent_app_number] => 10/765292 [patent_app_country] => US [patent_app_date] => 2004-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5379 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/937/06937511.pdf [firstpage_image] =>[orig_patent_app_number] => 10765292 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765292
Circuit and method for programming charge storage memory cells Jan 26, 2004 Issued
Array ( [id] => 7188952 [patent_doc_number] => 20050162924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Variable current sinking for coarse/fine programming of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 10/766786 [patent_app_country] => US [patent_app_date] => 2004-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14039 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162924.pdf [firstpage_image] =>[orig_patent_app_number] => 10766786 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766786
Variable current sinking for coarse/fine programming of non-volatile memory Jan 26, 2004 Issued
Array ( [id] => 5636138 [patent_doc_number] => 20060067111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Magnetic storage cell, magnetic memory device and magnetic memory device manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/542623 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 23492 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20060067111.pdf [firstpage_image] =>[orig_patent_app_number] => 10542623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/542623
Magnetic storage cell, magnetic memory device and magnetic memory device manufacturing method Jan 20, 2004 Issued
Array ( [id] => 728179 [patent_doc_number] => 07046577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Negative voltage word line decoder, having compact terminating elements' [patent_app_type] => utility [patent_app_number] => 10/760631 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 8522 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046577.pdf [firstpage_image] =>[orig_patent_app_number] => 10760631 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/760631
Negative voltage word line decoder, having compact terminating elements Jan 19, 2004 Issued
Array ( [id] => 518025 [patent_doc_number] => 07196964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Selectable memory word line deactivation' [patent_app_type] => utility [patent_app_number] => 10/759388 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2613 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196964.pdf [firstpage_image] =>[orig_patent_app_number] => 10759388 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/759388
Selectable memory word line deactivation Jan 14, 2004 Issued
Array ( [id] => 7293458 [patent_doc_number] => 20040213033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 10/754691 [patent_app_country] => US [patent_app_date] => 2004-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5608 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20040213033.pdf [firstpage_image] =>[orig_patent_app_number] => 10754691 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/754691
Ferroelectric memory device Jan 11, 2004 Issued
Array ( [id] => 704651 [patent_doc_number] => 07064971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Methods for saving power and area for content addressable memory devices' [patent_app_type] => utility [patent_app_number] => 10/752317 [patent_app_country] => US [patent_app_date] => 2004-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 34 [patent_no_of_words] => 12609 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064971.pdf [firstpage_image] =>[orig_patent_app_number] => 10752317 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/752317
Methods for saving power and area for content addressable memory devices Jan 4, 2004 Issued
Array ( [id] => 7257188 [patent_doc_number] => 20040240274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Semiconductor memory device with modified global input/output scheme' [patent_app_type] => new [patent_app_number] => 10/749892 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7450 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240274.pdf [firstpage_image] =>[orig_patent_app_number] => 10749892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749892
Semiconductor memory device with modified global input/output scheme Dec 30, 2003 Issued
Array ( [id] => 786512 [patent_doc_number] => 06990036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Method and apparatus for multiple row caches per bank' [patent_app_type] => utility [patent_app_number] => 10/749690 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990036.pdf [firstpage_image] =>[orig_patent_app_number] => 10749690 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749690
Method and apparatus for multiple row caches per bank Dec 29, 2003 Issued
Array ( [id] => 7380054 [patent_doc_number] => 20040179401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/747692 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6885 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20040179401.pdf [firstpage_image] =>[orig_patent_app_number] => 10747692 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747692
Semiconductor memory Dec 29, 2003 Issued
Array ( [id] => 754329 [patent_doc_number] => 07023745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Voltage detect mechanism' [patent_app_type] => utility [patent_app_number] => 10/747390 [patent_app_country] => US [patent_app_date] => 2003-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1644 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023745.pdf [firstpage_image] =>[orig_patent_app_number] => 10747390 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747390
Voltage detect mechanism Dec 28, 2003 Issued
Array ( [id] => 768638 [patent_doc_number] => 07009905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Method and apparatus to reduce bias temperature instability (BTI) effects' [patent_app_type] => utility [patent_app_number] => 10/744175 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9249 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009905.pdf [firstpage_image] =>[orig_patent_app_number] => 10744175 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744175
Method and apparatus to reduce bias temperature instability (BTI) effects Dec 22, 2003 Issued
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