Search

Michael Thanh Tran

Examiner (ID: 7715, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2511
Total Applications
3089
Issued Applications
2919
Pending Applications
108
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 771989 [patent_doc_number] => 07006368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories' [patent_app_type] => utility [patent_app_number] => 10/702489 [patent_app_country] => US [patent_app_date] => 2003-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5934 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/006/07006368.pdf [firstpage_image] =>[orig_patent_app_number] => 10702489 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/702489
Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories Nov 6, 2003 Issued
Array ( [id] => 7263289 [patent_doc_number] => 20040150901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Magnetic device and method of making the same' [patent_app_type] => new [patent_app_number] => 10/703151 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 8306 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150901.pdf [firstpage_image] =>[orig_patent_app_number] => 10703151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/703151
Magnetic device and method of making the same Nov 5, 2003 Issued
Array ( [id] => 7465133 [patent_doc_number] => 20040095809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Nonvolatile memory and method of erasing for nonvolatile memory' [patent_app_type] => new [patent_app_number] => 10/700592 [patent_app_country] => US [patent_app_date] => 2003-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5532 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095809.pdf [firstpage_image] =>[orig_patent_app_number] => 10700592 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/700592
Nonvolatile memory and method of erasing for nonvolatile memory Nov 4, 2003 Issued
Array ( [id] => 7331121 [patent_doc_number] => 20040130938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Semiconductor memory device and control method thereof' [patent_app_type] => new [patent_app_number] => 10/702790 [patent_app_country] => US [patent_app_date] => 2003-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7619 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20040130938.pdf [firstpage_image] =>[orig_patent_app_number] => 10702790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/702790
Semiconductor memory device and control method thereof Nov 4, 2003 Issued
Array ( [id] => 7358434 [patent_doc_number] => 20040090853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Integrated dynamic memory and operating method' [patent_app_type] => new [patent_app_number] => 10/699231 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090853.pdf [firstpage_image] =>[orig_patent_app_number] => 10699231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/699231
Integrated dynamic memory and operating method Oct 30, 2003 Issued
Array ( [id] => 7608846 [patent_doc_number] => 06999345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-14 [patent_title] => 'Method of sense and program verify without a reference cell for non-volatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/699331 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4347 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/999/06999345.pdf [firstpage_image] =>[orig_patent_app_number] => 10699331 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/699331
Method of sense and program verify without a reference cell for non-volatile semiconductor memory Oct 30, 2003 Issued
Array ( [id] => 961660 [patent_doc_number] => 06952374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'Memory device for rapid data access from memory cell' [patent_app_type] => utility [patent_app_number] => 10/699161 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3146 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952374.pdf [firstpage_image] =>[orig_patent_app_number] => 10699161 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/699161
Memory device for rapid data access from memory cell Oct 30, 2003 Issued
Array ( [id] => 1042112 [patent_doc_number] => 06870760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Method and system for performing readout utilizing a self reference scheme' [patent_app_type] => utility [patent_app_number] => 10/688290 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4412 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870760.pdf [firstpage_image] =>[orig_patent_app_number] => 10688290 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688290
Method and system for performing readout utilizing a self reference scheme Oct 15, 2003 Issued
Array ( [id] => 7371649 [patent_doc_number] => 20040079986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Memory cell array comprising individually addressable memory cells and method of making the same' [patent_app_type] => new [patent_app_number] => 10/680383 [patent_app_country] => US [patent_app_date] => 2003-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6204 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20040079986.pdf [firstpage_image] =>[orig_patent_app_number] => 10680383 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/680383
Memory cell array comprising individually addressable memory cells and method of making the same Oct 5, 2003 Issued
Array ( [id] => 944817 [patent_doc_number] => 06967873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Memory device and method using positive gate stress to recover overerased cell' [patent_app_type] => utility [patent_app_number] => 10/677790 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967873.pdf [firstpage_image] =>[orig_patent_app_number] => 10677790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/677790
Memory device and method using positive gate stress to recover overerased cell Oct 1, 2003 Issued
Array ( [id] => 862620 [patent_doc_number] => 07372758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Semiconductor memory device, method for controlling the same, and mobile electronic device' [patent_app_type] => utility [patent_app_number] => 10/529880 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 23728 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372758.pdf [firstpage_image] =>[orig_patent_app_number] => 10529880 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/529880
Semiconductor memory device, method for controlling the same, and mobile electronic device Oct 1, 2003 Issued
Array ( [id] => 7608827 [patent_doc_number] => 06999364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'DRAM circuit and its operation method' [patent_app_type] => utility [patent_app_number] => 10/605292 [patent_app_country] => US [patent_app_date] => 2003-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2792 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/999/06999364.pdf [firstpage_image] =>[orig_patent_app_number] => 10605292 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605292
DRAM circuit and its operation method Sep 18, 2003 Issued
Array ( [id] => 7268837 [patent_doc_number] => 20040057355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Variable level memory' [patent_app_type] => new [patent_app_number] => 10/666988 [patent_app_country] => US [patent_app_date] => 2003-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20040057355.pdf [firstpage_image] =>[orig_patent_app_number] => 10666988 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/666988
Variable level memory Sep 17, 2003 Issued
Array ( [id] => 7616113 [patent_doc_number] => 06947331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Method of erasing an EEPROM cell utilizing a frequency/time domain based erased signal' [patent_app_type] => utility [patent_app_number] => 10/665187 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 1786 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/947/06947331.pdf [firstpage_image] =>[orig_patent_app_number] => 10665187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/665187
Method of erasing an EEPROM cell utilizing a frequency/time domain based erased signal Sep 16, 2003 Issued
Array ( [id] => 7126225 [patent_doc_number] => 20050057969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 10/660789 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7749 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057969.pdf [firstpage_image] =>[orig_patent_app_number] => 10660789 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/660789
Nonvolatile semiconductor memory device Sep 11, 2003 Issued
Array ( [id] => 7200483 [patent_doc_number] => 20050052228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Non-volatile flash memory' [patent_app_type] => utility [patent_app_number] => 10/653892 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3854 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052228.pdf [firstpage_image] =>[orig_patent_app_number] => 10653892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653892
Non-volatile flash memory Sep 3, 2003 Issued
Array ( [id] => 7193587 [patent_doc_number] => 20040204891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Semiconductor memory device having a test mode for testing an operation state' [patent_app_type] => new [patent_app_number] => 10/653988 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8224 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20040204891.pdf [firstpage_image] =>[orig_patent_app_number] => 10653988 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653988
Semiconductor memory device having a test mode for testing an operation state Sep 3, 2003 Abandoned
Array ( [id] => 1016121 [patent_doc_number] => 06894927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Data writing and reading methods for flash memories and circuitry thereof' [patent_app_type] => utility [patent_app_number] => 10/654392 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2495 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894927.pdf [firstpage_image] =>[orig_patent_app_number] => 10654392 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654392
Data writing and reading methods for flash memories and circuitry thereof Sep 1, 2003 Issued
Array ( [id] => 7081839 [patent_doc_number] => 20050047219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Memory with reference-initiated sequential sensing' [patent_app_type] => utility [patent_app_number] => 10/650278 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5280 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20050047219.pdf [firstpage_image] =>[orig_patent_app_number] => 10650278 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/650278
Memory with reference-initiated sequential sensing Aug 27, 2003 Issued
Array ( [id] => 7115502 [patent_doc_number] => 20050068803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Method for controlling programming voltage levels of non-volatile memory cells, the method tracking the cell features, and corresponding voltage regulator' [patent_app_type] => utility [patent_app_number] => 10/651019 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5680 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20050068803.pdf [firstpage_image] =>[orig_patent_app_number] => 10651019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651019
Method for controlling programming voltage levels of non-volatile memory cells, the method tracking the cell features, and corresponding voltage regulator Aug 27, 2003 Issued
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