
Michael Thanh Tran
Examiner (ID: 2981, Phone: (571)272-1795 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827, 2511, 2818 |
| Total Applications | 3089 |
| Issued Applications | 2919 |
| Pending Applications | 108 |
| Abandoned Applications | 104 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 90/006699 | APPARATUS, SYSTEM AND METHOD FOR CONTROL OF SPEED OF OPERATION AND POWER CONSUMPTION OF A MEMORY | Jul 6, 2003 | Issued |
Array
(
[id] => 7628775
[patent_doc_number] => 06819584
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-16
[patent_title] => 'Nonvolatile ferroelectric memory device'
[patent_app_type] => B2
[patent_app_number] => 10/612987
[patent_app_country] => US
[patent_app_date] => 2003-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 2937
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 6
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/819/06819584.pdf
[firstpage_image] =>[orig_patent_app_number] => 10612987
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/612987 | Nonvolatile ferroelectric memory device | Jul 6, 2003 | Issued |
Array
(
[id] => 7360373
[patent_doc_number] => 20040004876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-08
[patent_title] => 'Circuit and method for selecting reference voltages in semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 10/612593
[patent_app_country] => US
[patent_app_date] => 2003-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4632
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20040004876.pdf
[firstpage_image] =>[orig_patent_app_number] => 10612593
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/612593 | Circuit and method for selecting reference voltages in semiconductor memory device | Jun 30, 2003 | Issued |
Array
(
[id] => 7374796
[patent_doc_number] => 20040027892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-12
[patent_title] => 'Semiconductor memory device with offset-compensated sensing scheme'
[patent_app_type] => new
[patent_app_number] => 10/611788
[patent_app_country] => US
[patent_app_date] => 2003-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7695
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20040027892.pdf
[firstpage_image] =>[orig_patent_app_number] => 10611788
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/611788 | Semiconductor memory device with offset-compensated sensing scheme | Jun 29, 2003 | Issued |
Array
(
[id] => 7415677
[patent_doc_number] => 20040264281
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Charge recycling decoder, method, and system'
[patent_app_type] => new
[patent_app_number] => 10/610490
[patent_app_country] => US
[patent_app_date] => 2003-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3586
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0264/20040264281.pdf
[firstpage_image] =>[orig_patent_app_number] => 10610490
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/610490 | Charge recycling decoder, method, and system | Jun 29, 2003 | Issued |
Array
(
[id] => 957009
[patent_doc_number] => 06956763
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-18
[patent_title] => 'MRAM element and methods for writing the MRAM element'
[patent_app_type] => utility
[patent_app_number] => 10/609288
[patent_app_country] => US
[patent_app_date] => 2003-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 41
[patent_no_of_words] => 5777
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/956/06956763.pdf
[firstpage_image] =>[orig_patent_app_number] => 10609288
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/609288 | MRAM element and methods for writing the MRAM element | Jun 26, 2003 | Issued |
Array
(
[id] => 7614395
[patent_doc_number] => 06898135
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-24
[patent_title] => 'Latch type sense amplifier method and apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/606587
[patent_app_country] => US
[patent_app_date] => 2003-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2098
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/898/06898135.pdf
[firstpage_image] =>[orig_patent_app_number] => 10606587
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/606587 | Latch type sense amplifier method and apparatus | Jun 25, 2003 | Issued |
Array
(
[id] => 7244127
[patent_doc_number] => 20040257877
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Source controlled operation of non-volatile memories'
[patent_app_type] => new
[patent_app_number] => 10/600988
[patent_app_country] => US
[patent_app_date] => 2003-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4742
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20040257877.pdf
[firstpage_image] =>[orig_patent_app_number] => 10600988
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/600988 | Source controlled operation of non-volatile memories | Jun 19, 2003 | Issued |
Array
(
[id] => 6648409
[patent_doc_number] => 20030212964
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Apparatus for optimized constraint characterization with degradation options and associated methods'
[patent_app_type] => new
[patent_app_number] => 10/465123
[patent_app_country] => US
[patent_app_date] => 2003-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 16857
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20030212964.pdf
[firstpage_image] =>[orig_patent_app_number] => 10465123
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/465123 | Apparatus for optimized constraint characterization with degradation options and associated methods | Jun 18, 2003 | Abandoned |
Array
(
[id] => 7225412
[patent_doc_number] => 20040156237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Block select circuit in a flash memory device'
[patent_app_type] => new
[patent_app_number] => 10/464666
[patent_app_country] => US
[patent_app_date] => 2003-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4499
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20040156237.pdf
[firstpage_image] =>[orig_patent_app_number] => 10464666
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/464666 | Block select circuit in a flash memory device | Jun 18, 2003 | Issued |
Array
(
[id] => 7325251
[patent_doc_number] => 20040252574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-16
[patent_title] => 'Word line transistor stacking for leakage control'
[patent_app_type] => new
[patent_app_number] => 10/461562
[patent_app_country] => US
[patent_app_date] => 2003-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1310
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0252/20040252574.pdf
[firstpage_image] =>[orig_patent_app_number] => 10461562
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/461562 | Word line transistor stacking for leakage control | Jun 11, 2003 | Issued |
Array
(
[id] => 1023685
[patent_doc_number] => 06888772
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Non-volatile memory device achieving fast data reading by reducing data line charging period'
[patent_app_type] => utility
[patent_app_number] => 10/458369
[patent_app_country] => US
[patent_app_date] => 2003-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 8639
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/888/06888772.pdf
[firstpage_image] =>[orig_patent_app_number] => 10458369
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/458369 | Non-volatile memory device achieving fast data reading by reducing data line charging period | Jun 10, 2003 | Issued |
Array
(
[id] => 942234
[patent_doc_number] => 06970383
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-11-29
[patent_title] => 'Methods of redundancy in a floating trap memory element based field programmable gate array'
[patent_app_type] => utility
[patent_app_number] => 10/459412
[patent_app_country] => US
[patent_app_date] => 2003-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5216
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/970/06970383.pdf
[firstpage_image] =>[orig_patent_app_number] => 10459412
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/459412 | Methods of redundancy in a floating trap memory element based field programmable gate array | Jun 9, 2003 | Issued |
Array
(
[id] => 6610845
[patent_doc_number] => 20030209730
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Leadframe inductors'
[patent_app_type] => new
[patent_app_number] => 10/456320
[patent_app_country] => US
[patent_app_date] => 2003-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2605
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20030209730.pdf
[firstpage_image] =>[orig_patent_app_number] => 10456320
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/456320 | Leadframe inductors | Jun 5, 2003 | Issued |
Array
(
[id] => 1135620
[patent_doc_number] => 06788572
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-07
[patent_title] => 'Non-volatile multi-level semiconductor flash memory device and method of driving same'
[patent_app_type] => B2
[patent_app_number] => 10/455409
[patent_app_country] => US
[patent_app_date] => 2003-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 26
[patent_no_of_words] => 11668
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/788/06788572.pdf
[firstpage_image] =>[orig_patent_app_number] => 10455409
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/455409 | Non-volatile multi-level semiconductor flash memory device and method of driving same | Jun 5, 2003 | Issued |
Array
(
[id] => 7463613
[patent_doc_number] => 20040120192
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-24
[patent_title] => 'Semiconductor memory device including power generation circuit implementing stable operation'
[patent_app_type] => new
[patent_app_number] => 10/455388
[patent_app_country] => US
[patent_app_date] => 2003-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9440
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20040120192.pdf
[firstpage_image] =>[orig_patent_app_number] => 10455388
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/455388 | Semiconductor memory device including power generation circuit implementing stable operation | Jun 5, 2003 | Issued |
Array
(
[id] => 249494
[patent_doc_number] => RE040894
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2009-09-01
[patent_title] => 'Sample and load scheme for observability internal nodes in a PLD'
[patent_app_type] => reissue
[patent_app_number] => 10/456356
[patent_app_country] => US
[patent_app_date] => 2003-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2915
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/040/RE040894.pdf
[firstpage_image] =>[orig_patent_app_number] => 10456356
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/456356 | Sample and load scheme for observability internal nodes in a PLD | Jun 4, 2003 | Issued |
Array
(
[id] => 7302472
[patent_doc_number] => 20040114449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-17
[patent_title] => 'Semiconductor memory device for improvement of defective data line relief rate'
[patent_app_type] => new
[patent_app_number] => 10/454666
[patent_app_country] => US
[patent_app_date] => 2003-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 11066
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 380
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0114/20040114449.pdf
[firstpage_image] =>[orig_patent_app_number] => 10454666
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/454666 | Semiconductor memory device for improvement of defective data line relief rate | Jun 4, 2003 | Issued |
Array
(
[id] => 7392515
[patent_doc_number] => 20040017702
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Storage element with a defined number of write cycles'
[patent_app_type] => new
[patent_app_number] => 10/453466
[patent_app_country] => US
[patent_app_date] => 2003-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3106
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20040017702.pdf
[firstpage_image] =>[orig_patent_app_number] => 10453466
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/453466 | Storage element with a defined number of write cycles | Jun 2, 2003 | Issued |
Array
(
[id] => 7338125
[patent_doc_number] => 20040190319
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'Content addressable memory and memory system'
[patent_app_type] => new
[patent_app_number] => 10/452288
[patent_app_country] => US
[patent_app_date] => 2003-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4477
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0190/20040190319.pdf
[firstpage_image] =>[orig_patent_app_number] => 10452288
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/452288 | Content addressable memory and memory system | Jun 2, 2003 | Issued |