Search

Michael Thanh Tran

Examiner (ID: 2981, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818
Total Applications
3089
Issued Applications
2919
Pending Applications
108
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7257205 [patent_doc_number] => 20040240282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Memory device with built-in error-correction capabilities' [patent_app_type] => new [patent_app_number] => 10/449590 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3997 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240282.pdf [firstpage_image] =>[orig_patent_app_number] => 10449590 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449590
Memory device with built-in error-correction capabilities Jun 1, 2003 Issued
Array ( [id] => 749332 [patent_doc_number] => 07027318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Method and system for adjusting offset voltage' [patent_app_type] => utility [patent_app_number] => 10/449572 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4052 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/027/07027318.pdf [firstpage_image] =>[orig_patent_app_number] => 10449572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449572
Method and system for adjusting offset voltage May 29, 2003 Issued
Array ( [id] => 7257202 [patent_doc_number] => 20040240280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Signal integrity checking circuit' [patent_app_type] => new [patent_app_number] => 10/452562 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1229 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240280.pdf [firstpage_image] =>[orig_patent_app_number] => 10452562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452562
Signal integrity checking circuit May 29, 2003 Issued
Array ( [id] => 1026555 [patent_doc_number] => 06885572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/449570 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 20327 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/885/06885572.pdf [firstpage_image] =>[orig_patent_app_number] => 10449570 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449570
Semiconductor memory device May 28, 2003 Issued
Array ( [id] => 1164467 [patent_doc_number] => 06762967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Semiconductor memory device having a circuit for fast operation' [patent_app_type] => B2 [patent_app_number] => 10/443775 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5571 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762967.pdf [firstpage_image] =>[orig_patent_app_number] => 10443775 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443775
Semiconductor memory device having a circuit for fast operation May 22, 2003 Issued
Array ( [id] => 7627364 [patent_doc_number] => 06807077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Content addressable memory capable of stably storing ternary data' [patent_app_type] => B2 [patent_app_number] => 10/442986 [patent_app_country] => US [patent_app_date] => 2003-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 39 [patent_no_of_words] => 29918 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807077.pdf [firstpage_image] =>[orig_patent_app_number] => 10442986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442986
Content addressable memory capable of stably storing ternary data May 21, 2003 Issued
Array ( [id] => 7465110 [patent_doc_number] => 20040095804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Thin film magnetic memory device provided with magnetic tunnel junctions' [patent_app_type] => new [patent_app_number] => 10/441088 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11386 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095804.pdf [firstpage_image] =>[orig_patent_app_number] => 10441088 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441088
Thin film magnetic memory device provided with magnetic tunnel junctions May 19, 2003 Issued
Array ( [id] => 7459177 [patent_doc_number] => 20040094780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Semiconductor memory device with structure of converting parallel data into serial data' [patent_app_type] => new [patent_app_number] => 10/440188 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16919 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20040094780.pdf [firstpage_image] =>[orig_patent_app_number] => 10440188 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/440188
Semiconductor memory device with structure of converting parallel data into serial data May 18, 2003 Issued
Array ( [id] => 6663077 [patent_doc_number] => 20030202403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Reducing the effects of noise in non-volatile memories through multiple reads' [patent_app_type] => new [patent_app_number] => 10/439508 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7566 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20030202403.pdf [firstpage_image] =>[orig_patent_app_number] => 10439508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439508
Reducing the effects of noise in non-volatile memories through multiple reads May 15, 2003 Issued
Array ( [id] => 6768904 [patent_doc_number] => 20030214844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Nonvolatile semiconductor memory device of virtual-ground memory array with reliable data reading' [patent_app_type] => new [patent_app_number] => 10/437390 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6619 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20030214844.pdf [firstpage_image] =>[orig_patent_app_number] => 10437390 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/437390
Nonvolatile semiconductor memory device of virtual-ground memory array with reliable data reading May 13, 2003 Issued
Array ( [id] => 6724150 [patent_doc_number] => 20030206462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Circuit and method for testing a ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 10/436801 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5269 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20030206462.pdf [firstpage_image] =>[orig_patent_app_number] => 10436801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436801
Circuit and method for testing a ferroelectric memory device May 11, 2003 Issued
Array ( [id] => 6700397 [patent_doc_number] => 20030223277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => new [patent_app_number] => 10/428586 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7204 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20030223277.pdf [firstpage_image] =>[orig_patent_app_number] => 10428586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428586
Semiconductor memory device Apr 30, 2003 Issued
Array ( [id] => 6916896 [patent_doc_number] => 20050094457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Ferroelectric memory and method of operating same' [patent_app_type] => utility [patent_app_number] => 10/425257 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12574 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20050094457.pdf [firstpage_image] =>[orig_patent_app_number] => 10425257 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425257
Ferroelectric memory and method of operating same Apr 27, 2003 Abandoned
Array ( [id] => 6724145 [patent_doc_number] => 20030206457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Semiconductor device having mechanism capable of high-speed operation' [patent_app_type] => new [patent_app_number] => 10/424104 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 61 [patent_no_of_words] => 28408 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20030206457.pdf [firstpage_image] =>[orig_patent_app_number] => 10424104 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/424104
Semiconductor device having mechanism capable of high-speed operation Apr 27, 2003 Issued
Array ( [id] => 1149453 [patent_doc_number] => 06778442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Method of dual cell memory device operation for improved end-of-life read margin' [patent_app_type] => B1 [patent_app_number] => 10/422092 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 8711 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/778/06778442.pdf [firstpage_image] =>[orig_patent_app_number] => 10422092 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422092
Method of dual cell memory device operation for improved end-of-life read margin Apr 23, 2003 Issued
Array ( [id] => 1099301 [patent_doc_number] => 06822909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of controlling program threshold voltage distribution of a dual cell memory device' [patent_app_type] => B1 [patent_app_number] => 10/422090 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 9865 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822909.pdf [firstpage_image] =>[orig_patent_app_number] => 10422090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422090
Method of controlling program threshold voltage distribution of a dual cell memory device Apr 23, 2003 Issued
Array ( [id] => 1184621 [patent_doc_number] => 06741514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Semiconductor memory device and method of controlling the same' [patent_app_type] => B2 [patent_app_number] => 10/420790 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7615 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/741/06741514.pdf [firstpage_image] =>[orig_patent_app_number] => 10420790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420790
Semiconductor memory device and method of controlling the same Apr 22, 2003 Issued
Array ( [id] => 7293445 [patent_doc_number] => 20040213027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'INTEGRATED CONTENT ADDRESSABLE MEMORY ARCHITECTURE' [patent_app_type] => new [patent_app_number] => 10/249588 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5865 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20040213027.pdf [firstpage_image] =>[orig_patent_app_number] => 10249588 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249588
Integrated content addressable memory architecture Apr 21, 2003 Issued
Array ( [id] => 6724138 [patent_doc_number] => 20030206450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Segmented metal bitlines' [patent_app_type] => new [patent_app_number] => 10/418416 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20030206450.pdf [firstpage_image] =>[orig_patent_app_number] => 10418416 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/418416
Segmented metal bitlines Apr 17, 2003 Issued
Array ( [id] => 7418940 [patent_doc_number] => 20040208062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Nonvolatile memory cell array' [patent_app_type] => new [patent_app_number] => 10/414089 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1349 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20040208062.pdf [firstpage_image] =>[orig_patent_app_number] => 10414089 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/414089
Nonvolatile memory cell array Apr 15, 2003 Abandoned
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