Michael Thanh Tran

Array ( [id] => 7628744 [patent_doc_number] => 06819616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Serial to parallel data input methods and related input buffers' [patent_app_type] => B2 [patent_app_number] => 10/337688 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4852 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819616.pdf [firstpage_image] =>[orig_patent_app_number] => 10337688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7346669 [patent_doc_number] => 20040047193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Nonvolatile ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 10/331586 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6761 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20040047193.pdf [firstpage_image] =>[orig_patent_app_number] => 10331586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6850373 [patent_doc_number] => 20030142575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Hole driver in semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/331791 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4213 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20030142575.pdf [firstpage_image] =>[orig_patent_app_number] => 10331791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7328632 [patent_doc_number] => 20040139271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Multi-ported register files' [patent_app_type] => new [patent_app_number] => 10/330652 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4182 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139271.pdf [firstpage_image] =>[orig_patent_app_number] => 10330652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1174214 [patent_doc_number] => 06757210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/330892 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2041 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757210.pdf [firstpage_image] =>[orig_patent_app_number] => 10330892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180241 [patent_doc_number] => 06751134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Internal voltage generating apparatus for a semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/330887 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3117 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751134.pdf [firstpage_image] =>[orig_patent_app_number] => 10330887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1057924 [patent_doc_number] => 06856538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Thin film magnetic memory device suppressing internal magnetic noises' [patent_app_type] => utility [patent_app_number] => 10/327888 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 37 [patent_no_of_words] => 20636 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856538.pdf [firstpage_image] =>[orig_patent_app_number] => 10327888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1145146 [patent_doc_number] => 06781869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 10/327890 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 75 [patent_no_of_words] => 10403 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781869.pdf [firstpage_image] =>[orig_patent_app_number] => 10327890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7297816 [patent_doc_number] => 20040125654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Programming flash memories' [patent_app_type] => new [patent_app_number] => 10/329792 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4868 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20040125654.pdf [firstpage_image] =>[orig_patent_app_number] => 10329792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7440953 [patent_doc_number] => 20040066684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/320686 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7057 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20040066684.pdf [firstpage_image] =>[orig_patent_app_number] => 10320686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6651923 [patent_doc_number] => 20030076722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Method and system for displaying VLSI layout data' [patent_app_type] => new [patent_app_number] => 10/314957 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16083 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20030076722.pdf [firstpage_image] =>[orig_patent_app_number] => 10314957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1208690 [patent_doc_number] => 06717871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Semiconductor device with flexible redundancy system' [patent_app_type] => B2 [patent_app_number] => 10/310960 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6278 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/717/06717871.pdf [firstpage_image] =>[orig_patent_app_number] => 10310960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7627355 [patent_doc_number] => 06807086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Magnetic random access memory' [patent_app_type] => B2 [patent_app_number] => 10/305988 [patent_app_country] => US [patent_app_date] => 2002-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 17959 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807086.pdf [firstpage_image] =>[orig_patent_app_number] => 10305988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1114836 [patent_doc_number] => 06804163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Semiconductor memory device for reducing chip size' [patent_app_type] => B2 [patent_app_number] => 10/305986 [patent_app_country] => US [patent_app_date] => 2002-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4631 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804163.pdf [firstpage_image] =>[orig_patent_app_number] => 10305986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1054777 [patent_doc_number] => 06859410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch' [patent_app_type] => utility [patent_app_number] => 10/306888 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9095 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859410.pdf [firstpage_image] =>[orig_patent_app_number] => 10306888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 554307 [patent_doc_number] => 07167386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Ferroelectric memory and operating method therefor' [patent_app_type] => utility [patent_app_number] => 10/304691 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 6896 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167386.pdf [firstpage_image] =>[orig_patent_app_number] => 10304691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7459449 [patent_doc_number] => 20040100828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Stacked memory device having shared bitlines and method of making the same' [patent_app_type] => new [patent_app_number] => 10/305588 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3610 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20040100828.pdf [firstpage_image] =>[orig_patent_app_number] => 10305588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6820770 [patent_doc_number] => 20030218931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Semiconductor memory device requiring refresh operation' [patent_app_type] => new [patent_app_number] => 10/300591 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10300 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20030218931.pdf [firstpage_image] =>[orig_patent_app_number] => 10300591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6636582 [patent_doc_number] => 20030103392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Method of controlling the operation of non-volatile semiconductor memory chips' [patent_app_type] => new [patent_app_number] => 10/298587 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 18068 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20030103392.pdf [firstpage_image] =>[orig_patent_app_number] => 10298587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7465233 [patent_doc_number] => 20040095826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'System and method for sensing memory cells of an array of memory cells' [patent_app_type] => new [patent_app_number] => 10/299288 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4919 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095826.pdf [firstpage_image] =>[orig_patent_app_number] => 10299288 [rel_patent_id] =>[rel_patent_doc_number] =>)