Search

Michael Thanh Tran

Examiner (ID: 2981, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818
Total Applications
3089
Issued Applications
2919
Pending Applications
108
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1199332 [patent_doc_number] => 06728147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method for on-chip testing of memory cells of an integrated memory circuit' [patent_app_type] => B2 [patent_app_number] => 10/202690 [patent_app_country] => US [patent_app_date] => 2002-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1712 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728147.pdf [firstpage_image] =>[orig_patent_app_number] => 10202690 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/202690
Method for on-chip testing of memory cells of an integrated memory circuit Jul 23, 2002 Issued
Array ( [id] => 1194917 [patent_doc_number] => 06731551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Testing memory using a stress signal' [patent_app_type] => B2 [patent_app_number] => 10/192390 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6472 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/731/06731551.pdf [firstpage_image] =>[orig_patent_app_number] => 10192390 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192390
Testing memory using a stress signal Jul 9, 2002 Issued
Array ( [id] => 6644034 [patent_doc_number] => 20030007387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'CG-WL voltage boosting scheme for twin MONOS' [patent_app_type] => new [patent_app_number] => 10/190690 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5019 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007387.pdf [firstpage_image] =>[orig_patent_app_number] => 10190690 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190690
CG-WL voltage boosting scheme for twin MONOS Jul 7, 2002 Issued
Array ( [id] => 7360385 [patent_doc_number] => 20040004880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'BIT LINE CONTROL AND SENSE AMPLIFICATION FOR TCCT-BASED MEMORY CELLS' [patent_app_type] => new [patent_app_number] => 10/191686 [patent_app_country] => US [patent_app_date] => 2002-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8656 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004880.pdf [firstpage_image] =>[orig_patent_app_number] => 10191686 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/191686
Bit line control and sense amplification for TCCT-based memory cells Jul 4, 2002 Issued
Array ( [id] => 7425636 [patent_doc_number] => 20040001351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Memory having a precharge circuit and method therefor' [patent_app_type] => new [patent_app_number] => 10/185488 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14347 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20040001351.pdf [firstpage_image] =>[orig_patent_app_number] => 10185488 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185488
Memory having a precharge circuit and method therefor Jun 27, 2002 Issued
Array ( [id] => 7425701 [patent_doc_number] => 20040001360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Memory architecture with write circuitry and method therefor' [patent_app_type] => new [patent_app_number] => 10/185888 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14237 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20040001360.pdf [firstpage_image] =>[orig_patent_app_number] => 10185888 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185888
Memory architecture with write circuitry and method therefor Jun 27, 2002 Issued
Array ( [id] => 6745244 [patent_doc_number] => 20030022427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'DRAM cell refreshment method and circuit' [patent_app_type] => new [patent_app_number] => 10/186289 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022427.pdf [firstpage_image] =>[orig_patent_app_number] => 10186289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186289
DRAM cell refreshment method and circuit Jun 26, 2002 Issued
Array ( [id] => 6734429 [patent_doc_number] => 20030012064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Method of refreshing an electrically erasable and programmable non-volatile memory' [patent_app_type] => new [patent_app_number] => 10/176387 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20030012064.pdf [firstpage_image] =>[orig_patent_app_number] => 10176387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/176387
Method of refreshing an electrically erasable and programmable non-volatile memory Jun 19, 2002 Issued
Array ( [id] => 1350080 [patent_doc_number] => 06590811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Higher program VT and faster programming rates based on improved erase methods' [patent_app_type] => B1 [patent_app_number] => 10/173262 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 13593 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590811.pdf [firstpage_image] =>[orig_patent_app_number] => 10173262 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/173262
Higher program VT and faster programming rates based on improved erase methods Jun 16, 2002 Issued
Array ( [id] => 1216067 [patent_doc_number] => 06711044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Semiconductor memory device with a countermeasure to a signal delay' [patent_app_type] => B2 [patent_app_number] => 10/171790 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 7009 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711044.pdf [firstpage_image] =>[orig_patent_app_number] => 10171790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/171790
Semiconductor memory device with a countermeasure to a signal delay Jun 16, 2002 Issued
Array ( [id] => 7623002 [patent_doc_number] => 06687163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Semiconductor memory arrangement' [patent_app_type] => B2 [patent_app_number] => 10/164190 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2072 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687163.pdf [firstpage_image] =>[orig_patent_app_number] => 10164190 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164190
Semiconductor memory arrangement Jun 5, 2002 Issued
Array ( [id] => 1325469 [patent_doc_number] => 06606270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing' [patent_app_type] => B2 [patent_app_number] => 10/162354 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2848 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606270.pdf [firstpage_image] =>[orig_patent_app_number] => 10162354 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162354
Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing Jun 2, 2002 Issued
Array ( [id] => 6154689 [patent_doc_number] => 20020145452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Differential sensing amplifier for content addressable memory' [patent_app_type] => new [patent_app_number] => 10/158475 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4850 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145452.pdf [firstpage_image] =>[orig_patent_app_number] => 10158475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/158475
Differential sensing amplifier for content addressable memory May 30, 2002 Issued
Array ( [id] => 6321085 [patent_doc_number] => 20020196683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Semiconductor integrated circuit device provided with a self-testing circuit for carrying out an\nanalysis for repair by using a redundant memory cell' [patent_app_type] => new [patent_app_number] => 10/152689 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 23266 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20020196683.pdf [firstpage_image] =>[orig_patent_app_number] => 10152689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152689
Semiconductor integrated circuit device provided with a self-testing circuit for carrying out an analysis for repair by using a redundant memory cell May 22, 2002 Issued
Array ( [id] => 6812621 [patent_doc_number] => 20030072171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Content addressable memory device' [patent_app_type] => new [patent_app_number] => 10/153391 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3807 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20030072171.pdf [firstpage_image] =>[orig_patent_app_number] => 10153391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/153391
Content addressable memory device May 21, 2002 Issued
Array ( [id] => 6321077 [patent_doc_number] => 20020196682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Memory device' [patent_app_type] => new [patent_app_number] => 10/151090 [patent_app_country] => US [patent_app_date] => 2002-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8971 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20020196682.pdf [firstpage_image] =>[orig_patent_app_number] => 10151090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/151090
Memory device May 19, 2002 Issued
Array ( [id] => 1199325 [patent_doc_number] => 06728143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Integrated memory' [patent_app_type] => B2 [patent_app_number] => 10/151088 [patent_app_country] => US [patent_app_date] => 2002-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2142 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728143.pdf [firstpage_image] =>[orig_patent_app_number] => 10151088 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/151088
Integrated memory May 19, 2002 Issued
Array ( [id] => 7630484 [patent_doc_number] => 06636452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Address control apparatus of semiconductor memory device using bank address' [patent_app_type] => B2 [patent_app_number] => 10/150090 [patent_app_country] => US [patent_app_date] => 2002-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2574 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636452.pdf [firstpage_image] =>[orig_patent_app_number] => 10150090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/150090
Address control apparatus of semiconductor memory device using bank address May 19, 2002 Issued
Array ( [id] => 7624494 [patent_doc_number] => 06724682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Nonvolatile semiconductor memory device having selective multiple-speed operation mode' [patent_app_type] => B2 [patent_app_number] => 10/150387 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724682.pdf [firstpage_image] =>[orig_patent_app_number] => 10150387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/150387
Nonvolatile semiconductor memory device having selective multiple-speed operation mode May 16, 2002 Issued
Array ( [id] => 6782050 [patent_doc_number] => 20030063497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => '256 meg dynamic random access memory' [patent_app_type] => new [patent_app_number] => 10/147521 [patent_app_country] => US [patent_app_date] => 2002-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 368 [patent_figures_cnt] => 368 [patent_no_of_words] => 48689 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20030063497.pdf [firstpage_image] =>[orig_patent_app_number] => 10147521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/147521
256 Meg dynamic random access memory May 15, 2002 Issued
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