Search

Michael Thanh Tran

Examiner (ID: 3826, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2511
Total Applications
3148
Issued Applications
2945
Pending Applications
134
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17582607 [patent_doc_number] => 20220139462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => CONTROL METHOD AND CONTROLLER OF PROGRAM SUSPENDING AND RESUMING FOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/573532 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573532
Control method and controller of program suspending and resuming for memory Jan 10, 2022 Issued
Array ( [id] => 19046484 [patent_doc_number] => 11935603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Erase power loss indicator (EPLI) implementation in flash memory device [patent_app_type] => utility [patent_app_number] => 17/572881 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572881
Erase power loss indicator (EPLI) implementation in flash memory device Jan 10, 2022 Issued
Array ( [id] => 19168276 [patent_doc_number] => 11984187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Dynamic allocation of a capacitive component in a memory device [patent_app_type] => utility [patent_app_number] => 17/569303 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13434 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569303 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569303
Dynamic allocation of a capacitive component in a memory device Jan 4, 2022 Issued
Array ( [id] => 17536471 [patent_doc_number] => 20220115080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/560980 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560980 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560980
Semiconductor storage device Dec 22, 2021 Issued
Array ( [id] => 20160458 [patent_doc_number] => 12387090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Neuron simulation circuit and neural network apparatus [patent_app_type] => utility [patent_app_number] => 17/560801 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 3315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560801
Neuron simulation circuit and neural network apparatus Dec 22, 2021 Issued
Array ( [id] => 18455854 [patent_doc_number] => 20230197135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => EMBEDDED MEMORY IC'S WITH POWER SUPPLY DROOP CIRCUITRY COUPLED TO FERROELECTRIC CAPACITORS [patent_app_type] => utility [patent_app_number] => 17/558440 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558440 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558440
Embedded memory IC's with power supply droop circuitry coupled to ferroelectric capacitors Dec 20, 2021 Issued
Array ( [id] => 18455843 [patent_doc_number] => 20230197124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => MULTI-PORT SDRAM [patent_app_type] => utility [patent_app_number] => 17/644770 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644770
Multi-port SDRAM Dec 15, 2021 Issued
Array ( [id] => 18234899 [patent_doc_number] => 11599458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Stacked memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/551707 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551707 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551707
Stacked memory device and operating method thereof Dec 14, 2021 Issued
Array ( [id] => 19079266 [patent_doc_number] => 11948641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Control method and controller of 3D NAND flash [patent_app_type] => utility [patent_app_number] => 17/547197 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547197
Control method and controller of 3D NAND flash Dec 8, 2021 Issued
Array ( [id] => 17507317 [patent_doc_number] => 20220100420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => APPARATUS WITH ACCESS CONTROL MECHANISM AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/545220 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545220
Apparatus with access control mechanism and methods for operating the same Dec 7, 2021 Issued
Array ( [id] => 18985509 [patent_doc_number] => 11910722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Subtractive top via as a bottom electrode contact for an embedded memory [patent_app_type] => utility [patent_app_number] => 17/542696 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7253 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542696
Subtractive top via as a bottom electrode contact for an embedded memory Dec 5, 2021 Issued
Array ( [id] => 18423665 [patent_doc_number] => 20230178129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => DIELECTRIC FILL FOR TIGHT PITCH MRAM PILLAR ARRAY [patent_app_type] => utility [patent_app_number] => 17/541401 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541401
Dielectric fill for tight pitch MRAM pillar array Dec 2, 2021 Issued
Array ( [id] => 17485657 [patent_doc_number] => 20220093161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/457077 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457077
Memory device and operation method thereof Nov 30, 2021 Issued
Array ( [id] => 18408683 [patent_doc_number] => 20230170036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => ENVIRONMENTAL CONDITION TRACKING FOR A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/456972 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456972
Environmental condition tracking for a memory system Nov 29, 2021 Issued
Array ( [id] => 18394552 [patent_doc_number] => 20230162773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => Memory Device with Spin-Harvesting Structure [patent_app_type] => utility [patent_app_number] => 17/456088 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456088 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456088
Memory device with spin-harvesting structure Nov 21, 2021 Issued
Array ( [id] => 19639496 [patent_doc_number] => 12170109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Hybrid resistive memory [patent_app_type] => utility [patent_app_number] => 17/454311 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4111 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454311 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454311
Hybrid resistive memory Nov 9, 2021 Issued
Array ( [id] => 19123383 [patent_doc_number] => 11967377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Dynamically gated search lines for low-power multi-stage content addressable memory [patent_app_type] => utility [patent_app_number] => 17/522214 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4830 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522214
Dynamically gated search lines for low-power multi-stage content addressable memory Nov 8, 2021 Issued
Array ( [id] => 20495163 [patent_doc_number] => 12537039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/035013 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 61 [patent_no_of_words] => 35573 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18035013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/035013
Semiconductor device Nov 8, 2021 Issued
Array ( [id] => 18207351 [patent_doc_number] => 20230053608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => HYBRID MEMORY SYSTEM CONFIGURABLE TO STORE NEURAL MEMORY WEIGHT DATA IN ANALOG FORM OR DIGITAL FORM [patent_app_type] => utility [patent_app_number] => 17/519241 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519241
Hybrid memory system configurable to store neural memory weight data in analog form or digital form Nov 3, 2021 Issued
Array ( [id] => 17917211 [patent_doc_number] => 20220319607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => PROGRAMMING FOR THREE-DIMENSIONAL NAND MEMORY [patent_app_type] => utility [patent_app_number] => 17/518783 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518783 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518783
Programming for three-dimensional NAND memory Nov 3, 2021 Issued
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