Search

Michael Thanh Tran

Examiner (ID: 149, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818
Total Applications
3177
Issued Applications
2960
Pending Applications
145
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18271606 [patent_doc_number] => 20230092848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MULTI-DECK NON-VOLATILE MEMORY ARCHITECTURE WITH REDUCED TERMINATION TILE AREA [patent_app_type] => utility [patent_app_number] => 17/482578 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482578
Multi-deck non-volatile memory architecture with reduced termination tile area Sep 22, 2021 Issued
Array ( [id] => 18669710 [patent_doc_number] => 11776620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Memory device including semiconductor element [patent_app_type] => utility [patent_app_number] => 17/478282 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 107 [patent_no_of_words] => 22367 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478282
Memory device including semiconductor element Sep 16, 2021 Issued
Array ( [id] => 17447852 [patent_doc_number] => 20220068357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SENSE AMPLIFIER, MEMORY AND METHOD FOR CONTROLLING SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/472157 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472157
Sense amplifier, memory and method for controlling sense amplifier Sep 9, 2021 Issued
Array ( [id] => 19123399 [patent_doc_number] => 11967393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Method and apparatus for power saving in semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/472542 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472542
Method and apparatus for power saving in semiconductor devices Sep 9, 2021 Issued
Array ( [id] => 17870421 [patent_doc_number] => 20220293158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 17/470854 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470854
Semiconductor memory devices and methods of manufacturing thereof Sep 8, 2021 Issued
Array ( [id] => 18712540 [patent_doc_number] => 20230335173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/025457 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 66320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18025457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/025457
Semiconductor device and electronic device Sep 7, 2021 Issued
Array ( [id] => 17917163 [patent_doc_number] => 20220319559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => MEMORY CIRCUIT, MEMORY PRECHARGE CONTROL METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/446958 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 514 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446958 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446958
Memory circuit, memory precharge control method and device Sep 2, 2021 Issued
Array ( [id] => 17477070 [patent_doc_number] => 20220084574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => MAGNETIC MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/465080 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/465080
Magnetic memory device and memory system Sep 1, 2021 Issued
Array ( [id] => 19858045 [patent_doc_number] => 12260895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Apparatus with power-based data protection mechanism and methods for operating the same [patent_app_type] => utility [patent_app_number] => 17/464671 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5704 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464671 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464671
Apparatus with power-based data protection mechanism and methods for operating the same Aug 31, 2021 Issued
Array ( [id] => 17508826 [patent_doc_number] => 20220101929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/462013 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462013
Memory apparatus Aug 30, 2021 Issued
Array ( [id] => 17699987 [patent_doc_number] => 11373719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-28 [patent_title] => Contact layer traces to program programmable ROM [patent_app_type] => utility [patent_app_number] => 17/460368 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460368
Contact layer traces to program programmable ROM Aug 29, 2021 Issued
Array ( [id] => 18796992 [patent_doc_number] => 11830827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Semiconductor memory devices with dielectric fin structures [patent_app_type] => utility [patent_app_number] => 17/460652 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460652
Semiconductor memory devices with dielectric fin structures Aug 29, 2021 Issued
Array ( [id] => 18276903 [patent_doc_number] => 11615849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Memory device and programming method thereof [patent_app_type] => utility [patent_app_number] => 17/459371 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5235 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459371
Memory device and programming method thereof Aug 26, 2021 Issued
Array ( [id] => 18781078 [patent_doc_number] => 11822818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Memory device, image processing chip, and memory control method [patent_app_type] => utility [patent_app_number] => 17/458634 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458634 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458634
Memory device, image processing chip, and memory control method Aug 26, 2021 Issued
Array ( [id] => 18415796 [patent_doc_number] => 11670341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Multi-die peak power management for three-dimensional memory [patent_app_type] => utility [patent_app_number] => 17/411902 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7064 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411902
Multi-die peak power management for three-dimensional memory Aug 24, 2021 Issued
Array ( [id] => 17463408 [patent_doc_number] => 20220076714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => Methods and Circuits for Streaming Data to Processing Elements in Stacked Processor-Plus-Memory Architecture [patent_app_type] => utility [patent_app_number] => 17/410786 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410786 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410786
Methods and circuits for streaming data to processing elements in stacked processor-plus-memory architecture Aug 23, 2021 Issued
Array ( [id] => 18783944 [patent_doc_number] => 11825753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Memory cell, integrated circuit, and manufacturing method of memory cell [patent_app_type] => utility [patent_app_number] => 17/407105 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 9165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407105 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407105
Memory cell, integrated circuit, and manufacturing method of memory cell Aug 18, 2021 Issued
Array ( [id] => 17277661 [patent_doc_number] => 20210383859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SRAM DEVICES WITH REDUCED COUPLING CAPACITANCE [patent_app_type] => utility [patent_app_number] => 17/407005 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407005
SRAM devices with reduced coupling capacitance Aug 18, 2021 Issued
Array ( [id] => 18209873 [patent_doc_number] => 20230056133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => TEMPERATURE EXPOSURE DETECTION BASED ON MEMORY CELL RETENTION ERROR RATE [patent_app_type] => utility [patent_app_number] => 17/405633 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405633
Temperature exposure detection based on memory cell retention error rate Aug 17, 2021 Issued
Array ( [id] => 17447874 [patent_doc_number] => 20220068379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SYNAPSE AND SYNAPTIC ARRAY, AND COMPUTING SYSTEM USING THE SAME AND DRIVING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/405174 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405174
Synapse and synaptic array, and computing system using the same and driving method thereof Aug 17, 2021 Issued
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