Search

Michael Thanh Tran

Examiner (ID: 5527, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818
Total Applications
3128
Issued Applications
2940
Pending Applications
121
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19574847 [patent_doc_number] => 20240379139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/783345 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783345
SEMICONDUCTOR MEMORY DEVICE Jul 23, 2024 Pending
Array ( [id] => 19726887 [patent_doc_number] => 20250029638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MEMORY DEVICE INCLUDING 2-TRANSISTOR MEMORY CELL STRUCTURE FOR NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/778321 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778321
MEMORY DEVICE INCLUDING 2-TRANSISTOR MEMORY CELL STRUCTURE FOR NEURAL NETWORK Jul 18, 2024 Pending
Array ( [id] => 19548648 [patent_doc_number] => 20240365684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT, SPIN CURRENT MAGNETIZATION ROTATIONAL TYPE MAGNETORESISTIVE ELEMENT, MAGNETIC MEMORY, AND MAGNETIZATION ROTATION METHOD [patent_app_type] => utility [patent_app_number] => 18/771471 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771471
SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT, SPIN CURRENT MAGNETIZATION ROTATIONAL TYPE MAGNETORESISTIVE ELEMENT, MAGNETIC MEMORY, AND MAGNETIZATION ROTATION METHOD Jul 11, 2024 Pending
Array ( [id] => 20475965 [patent_doc_number] => 20260018186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => HANDLING WRITE COMMANDS DURING A REFRESH OPERATION IN A SHINGLED MAGNETIC RECORDING DRIVE [patent_app_type] => utility [patent_app_number] => 18/769628 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769628 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769628
HANDLING WRITE COMMANDS DURING A REFRESH OPERATION IN A SHINGLED MAGNETIC RECORDING DRIVE Jul 10, 2024 Pending
Array ( [id] => 20422857 [patent_doc_number] => 20250384942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/770583 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770583
ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT Jul 10, 2024 Pending
Array ( [id] => 19546133 [patent_doc_number] => 20240363169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE AND ERASING AND VERIFICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/765164 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/765164
MEMORY DEVICE AND ERASING AND VERIFICATION METHOD THEREOF Jul 4, 2024 Pending
Array ( [id] => 19546118 [patent_doc_number] => 20240363154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE WITH TUNABLE PROBABILISTIC STATE [patent_app_type] => utility [patent_app_number] => 18/763040 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763040
MEMORY DEVICE WITH TUNABLE PROBABILISTIC STATE Jul 2, 2024 Pending
Array ( [id] => 20019302 [patent_doc_number] => 20250157524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/754855 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754855 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754855
SEMICONDUCTOR MEMORY DEVICE Jun 25, 2024 Pending
Array ( [id] => 20071854 [patent_doc_number] => 20250210076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/750232 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750232 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/750232
SEMICONDUCTOR DEVICE Jun 20, 2024 Pending
Array ( [id] => 19820742 [patent_doc_number] => 20250078949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => APPARATUSES AND METHODS FOR HALF-PAGE MODES OF MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/745577 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745577 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745577
APPARATUSES AND METHODS FOR HALF-PAGE MODES OF MEMORY DEVICES Jun 16, 2024 Pending
Array ( [id] => 19483715 [patent_doc_number] => 20240331757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/740242 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740242
INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES Jun 10, 2024 Pending
Array ( [id] => 19694980 [patent_doc_number] => 20250013525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => LEARNED TEMPERATURE COMPENSATION [patent_app_type] => utility [patent_app_number] => 18/737831 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737831 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/737831
LEARNED TEMPERATURE COMPENSATION Jun 6, 2024 Pending
Array ( [id] => 20063097 [patent_doc_number] => 20250201319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => OPERATING METHOD OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/733182 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733182 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733182
OPERATING METHOD OF MEMORY DEVICE Jun 3, 2024 Pending
Array ( [id] => 20399036 [patent_doc_number] => 20250374511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY WITH BITCELL-TO-PERIPHERY INTERFACE TAP CELL [patent_app_type] => utility [patent_app_number] => 18/680474 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680474
MEMORY WITH BITCELL-TO-PERIPHERY INTERFACE TAP CELL May 30, 2024 Pending
Array ( [id] => 19603297 [patent_doc_number] => 20240394177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS [patent_app_type] => utility [patent_app_number] => 18/675127 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 666 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675127
MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS May 26, 2024 Pending
Array ( [id] => 19452369 [patent_doc_number] => 20240312499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => DIE LOCATION DETECTION FOR GROUPED MEMORY DIES [patent_app_type] => utility [patent_app_number] => 18/672339 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672339
DIE LOCATION DETECTION FOR GROUPED MEMORY DIES May 22, 2024 Pending
Array ( [id] => 19467675 [patent_doc_number] => 20240321345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SRAM STRUCTURE WITH ASYMMETRIC INTERCONNECTION [patent_app_type] => utility [patent_app_number] => 18/672090 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672090 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672090
SRAM STRUCTURE WITH ASYMMETRIC INTERCONNECTION May 22, 2024 Pending
Array ( [id] => 20581191 [patent_doc_number] => 12573445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/670780 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670780
Memory device May 21, 2024 Issued
Array ( [id] => 20305193 [patent_doc_number] => 12451189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Partial block handling protocol in a non-volatile memory device [patent_app_type] => utility [patent_app_number] => 18/670073 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670073
Partial block handling protocol in a non-volatile memory device May 20, 2024 Issued
Array ( [id] => 19589387 [patent_doc_number] => 20240386944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => MEMORY DEVICE USING SEMICONDUCTOR ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/662248 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 533 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662248 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662248
MEMORY DEVICE USING SEMICONDUCTOR ELEMENTS May 12, 2024 Pending
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