Search

Michael Thanh Tran

Examiner (ID: 149, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818
Total Applications
3177
Issued Applications
2960
Pending Applications
145
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16765283 [patent_doc_number] => 20210110865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => EXTENDING OPERATING TEMPERATURE OF STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/601236 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601236
Extending operating temperature of storage device Oct 13, 2019 Issued
Array ( [id] => 16653140 [patent_doc_number] => 10930331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Semiconductor device and operating method of a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/599692 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 8927 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599692
Semiconductor device and operating method of a semiconductor device Oct 10, 2019 Issued
Array ( [id] => 15442233 [patent_doc_number] => 20200035300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY [patent_app_type] => utility [patent_app_number] => 16/593530 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16593530 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/593530
Multistage set procedure for phase change memory Oct 3, 2019 Issued
Array ( [id] => 16339072 [patent_doc_number] => 10790039 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-29 [patent_title] => Semiconductor device having a test circuit [patent_app_type] => utility [patent_app_number] => 16/584520 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584520 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584520
Semiconductor device having a test circuit Sep 25, 2019 Issued
Array ( [id] => 16432697 [patent_doc_number] => 10832790 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Performance of non data word line maintenance in sub block mode [patent_app_type] => utility [patent_app_number] => 16/584684 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4832 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584684 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584684
Performance of non data word line maintenance in sub block mode Sep 25, 2019 Issued
Array ( [id] => 16479321 [patent_doc_number] => 10854274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Apparatuses and methods for dynamic timing of row pull down operations [patent_app_type] => utility [patent_app_number] => 16/584746 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7346 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584746 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584746
Apparatuses and methods for dynamic timing of row pull down operations Sep 25, 2019 Issued
Array ( [id] => 16668224 [patent_doc_number] => 10937477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Shared decoder circuit and method [patent_app_type] => utility [patent_app_number] => 16/582514 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 15327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582514 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582514
Shared decoder circuit and method Sep 24, 2019 Issued
Array ( [id] => 16528488 [patent_doc_number] => 20200402569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => METHODS FOR ADJUSTING MEMORY DEVICE REFRESH OPERATIONS BASED ON MEMORY DEVICE TEMPERATURE, AND RELATED MEMORY DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/567155 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567155 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567155
Methods for adjusting memory device refresh operations based on memory device temperature, and related memory devices and systems Sep 10, 2019 Issued
Array ( [id] => 16201739 [patent_doc_number] => 10726914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Programmable resistive memories with low power read operation and novel sensing scheme [patent_app_type] => utility [patent_app_number] => 16/559560 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6988 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559560 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559560
Programmable resistive memories with low power read operation and novel sensing scheme Sep 2, 2019 Issued
Array ( [id] => 16300832 [patent_doc_number] => 20200286555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/557872 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557872 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557872
Semiconductor memory device Aug 29, 2019 Issued
Array ( [id] => 16315845 [patent_doc_number] => 20200294583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/557876 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557876 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557876
Semiconductor memory device Aug 29, 2019 Issued
Array ( [id] => 16315847 [patent_doc_number] => 20200294585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/557818 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557818
Semiconductor storage device Aug 29, 2019 Issued
Array ( [id] => 16675689 [patent_doc_number] => 20210064455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => Error correction for content-addressable memory [patent_app_type] => utility [patent_app_number] => 16/553731 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553731 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553731
Error control for content-addressable memory Aug 27, 2019 Issued
Array ( [id] => 16324008 [patent_doc_number] => 10783978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-22 [patent_title] => Read voltage-assisted manufacturing tests of memory sub-system [patent_app_type] => utility [patent_app_number] => 16/551950 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551950
Read voltage-assisted manufacturing tests of memory sub-system Aug 26, 2019 Issued
Array ( [id] => 16172581 [patent_doc_number] => 10714157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-14 [patent_title] => Non-volatile memory and reset method thereof [patent_app_type] => utility [patent_app_number] => 16/551752 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551752
Non-volatile memory and reset method thereof Aug 26, 2019 Issued
Array ( [id] => 16566658 [patent_doc_number] => 10892032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-12 [patent_title] => Write and read common leveling for 4-bit wide DRAMS [patent_app_type] => utility [patent_app_number] => 16/536183 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536183 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536183
Write and read common leveling for 4-bit wide DRAMS Aug 7, 2019 Issued
Array ( [id] => 16409785 [patent_doc_number] => 10818348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/533043 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 15623 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533043 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533043
Semiconductor memory device Aug 5, 2019 Issued
Array ( [id] => 16432666 [patent_doc_number] => 10832759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Half-width, double pumped data path [patent_app_type] => utility [patent_app_number] => 16/526681 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6929 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526681 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526681
Half-width, double pumped data path Jul 29, 2019 Issued
Array ( [id] => 15502839 [patent_doc_number] => 20200051608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => SYSTEMS AND METHODS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL VOLTAGE BOOSTING [patent_app_type] => utility [patent_app_number] => 16/523653 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523653
Systems and methods for dynamic random access memory (DRAM) cell voltage boosting Jul 25, 2019 Issued
Array ( [id] => 16409793 [patent_doc_number] => 10818357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Memory device including multiple select gates and different bias conditions [patent_app_type] => utility [patent_app_number] => 16/518687 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 63 [patent_no_of_words] => 21389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518687 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518687
Memory device including multiple select gates and different bias conditions Jul 21, 2019 Issued
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