Michael Thanh Tran

Array ( [id] => 20530166 [patent_doc_number] => 12548607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Dynamic control of data transient rise time based on process, temperature, voltage (PVT) data in a memory device [patent_app_type] => utility [patent_app_number] => 18/653596 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3873 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20404285 [patent_doc_number] => 12494265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => On-access error correction for content-addressable memory [patent_app_type] => utility [patent_app_number] => 18/645939 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19974099 [patent_doc_number] => 12342734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Phase-change memory [patent_app_type] => utility [patent_app_number] => 18/646334 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19633000 [patent_doc_number] => 20240411449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => MANAGING PROGRAMMING OPERATION SEQUENCE IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/646266 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646266 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19559618 [patent_doc_number] => 20240371410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => APPARATUS INCLUDING MULTIPLE HIGH BANDWIDTH MEMORY CUBES [patent_app_type] => utility [patent_app_number] => 18/642796 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20104619 [patent_doc_number] => 20250234555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/641435 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19618912 [patent_doc_number] => 20240404592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => PROGRAMMABLE INTERPOSERS FOR ELECTRICALLY CONNECTING INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/640569 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20235521 [patent_doc_number] => 20250292840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => METHOD FOR CORRUPTING DATA STORED IN A MEMORY, AND CORRESPONDING INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/635767 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19348877 [patent_doc_number] => 20240257841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => DYNAMIC ALLOCATION OF A CAPACITIVE COMPONENT IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/634074 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20111282 [patent_doc_number] => 12362017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Memory device with reduced area [patent_app_type] => utility [patent_app_number] => 18/632856 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20332585 [patent_doc_number] => 12462869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Memory structure, manufacturing method thereof, operating method thereof, and memory array [patent_app_type] => utility [patent_app_number] => 18/619416 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20146612 [patent_doc_number] => 12380958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor memory structure [patent_app_type] => utility [patent_app_number] => 18/614180 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19305201 [patent_doc_number] => 20240233781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => METHOD AND APPARATUS FOR POWER SAVING IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/610880 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19283678 [patent_doc_number] => 20240220154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => ARRAY OF NON-VOLATILE MEMORY CELLS TO STORE DATA IN ANALOG FORM AND DIGITAL FORM [patent_app_type] => utility [patent_app_number] => 18/604884 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19952780 [patent_doc_number] => 12324165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Methods of writing and forming memory device [patent_app_type] => utility [patent_app_number] => 18/601994 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19455013 [patent_doc_number] => 20240315143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MAGNETIC MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/599458 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19992495 [patent_doc_number] => 20250130717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => STORAGE DEVICE AND MEMORY CONTROL DEVICE [patent_app_type] => utility [patent_app_number] => 18/597949 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20209431 [patent_doc_number] => 20250279151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => SELF-LEARNING BUILT-IN SELF-TEST (BIST) FOR LEAK DETECTION IN NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/594800 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20537347 [patent_doc_number] => 12554423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Accelerated programming of four gate, split-gate flash memory cells [patent_app_type] => utility [patent_app_number] => 18/594492 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19842526 [patent_doc_number] => 12254925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Control method and controller of 3D NAND flash [patent_app_type] => utility [patent_app_number] => 18/590207 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590207 [rel_patent_id] =>[rel_patent_doc_number] =>)