
Michael Thanh Tran
Examiner (ID: 149, Phone: (571)272-1795 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827, 2511, 2818 |
| Total Applications | 3177 |
| Issued Applications | 2960 |
| Pending Applications | 145 |
| Abandoned Applications | 104 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19586611
[patent_doc_number] => 20240384168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => MANAGING COMPENSATION FOR CELL-TO-CELL COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES USING SEGMENTATION
[patent_app_type] => utility
[patent_app_number] => 18/785912
[patent_app_country] => US
[patent_app_date] => 2024-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14178
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785912
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/785912 | MANAGING COMPENSATION FOR CELL-TO-CELL COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES USING SEGMENTATION | Jul 25, 2024 | Pending |
Array
(
[id] => 20010858
[patent_doc_number] => 20250149080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => MEMORY DEVICE FOR CONTROLLING SHIELDING BIT LINES
[patent_app_type] => utility
[patent_app_number] => 18/784796
[patent_app_country] => US
[patent_app_date] => 2024-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7481
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784796
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/784796 | MEMORY DEVICE FOR CONTROLLING SHIELDING BIT LINES | Jul 24, 2024 | Pending |
Array
(
[id] => 20820698
[patent_doc_number] => 12676171
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-07-07
[patent_title] => Semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 18/783345
[patent_app_country] => US
[patent_app_date] => 2024-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 31
[patent_no_of_words] => 17631
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783345
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/783345 | Semiconductor memory device | Jul 23, 2024 | Issued |
Array
(
[id] => 20746617
[patent_doc_number] => 12646536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-02
[patent_title] => Memory device including 2-transistor memory cell structure for neural network
[patent_app_type] => utility
[patent_app_number] => 18/778321
[patent_app_country] => US
[patent_app_date] => 2024-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 15041
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778321
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/778321 | Memory device including 2-transistor memory cell structure for neural network | Jul 18, 2024 | Issued |
Array
(
[id] => 19548648
[patent_doc_number] => 20240365684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT, SPIN CURRENT MAGNETIZATION ROTATIONAL TYPE MAGNETORESISTIVE ELEMENT, MAGNETIC MEMORY, AND MAGNETIZATION ROTATION METHOD
[patent_app_type] => utility
[patent_app_number] => 18/771471
[patent_app_country] => US
[patent_app_date] => 2024-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11446
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771471
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/771471 | SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT, SPIN CURRENT MAGNETIZATION ROTATIONAL TYPE MAGNETORESISTIVE ELEMENT, MAGNETIC MEMORY, AND MAGNETIZATION ROTATION METHOD | Jul 11, 2024 | Pending |
Array
(
[id] => 20732905
[patent_doc_number] => 12640165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-26
[patent_title] => Handling write commands during a refresh operation in a shingled magnetic recording drive
[patent_app_type] => utility
[patent_app_number] => 18/769628
[patent_app_country] => US
[patent_app_date] => 2024-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 27
[patent_no_of_words] => 6817
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769628
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/769628 | Handling write commands during a refresh operation in a shingled magnetic recording drive | Jul 10, 2024 | Issued |
Array
(
[id] => 20422857
[patent_doc_number] => 20250384942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-18
[patent_title] => ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT
[patent_app_type] => utility
[patent_app_number] => 18/770583
[patent_app_country] => US
[patent_app_date] => 2024-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4726
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770583
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/770583 | ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT | Jul 10, 2024 | Pending |
Array
(
[id] => 20807376
[patent_doc_number] => 12672295
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-30
[patent_title] => Three dimensional semiconductor device stack, system having the same, and method of operating three dimensional semiconductor device stack
[patent_app_type] => utility
[patent_app_number] => 18/766708
[patent_app_country] => US
[patent_app_date] => 2024-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 764
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766708
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/766708 | Three dimensional semiconductor device stack, system having the same, and method of operating three dimensional semiconductor device stack | Jul 8, 2024 | Issued |
Array
(
[id] => 19546133
[patent_doc_number] => 20240363169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => MEMORY DEVICE AND ERASING AND VERIFICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/765164
[patent_app_country] => US
[patent_app_date] => 2024-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4045
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765164
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/765164 | MEMORY DEVICE AND ERASING AND VERIFICATION METHOD THEREOF | Jul 4, 2024 | Pending |
Array
(
[id] => 19546118
[patent_doc_number] => 20240363154
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => MEMORY DEVICE WITH TUNABLE PROBABILISTIC STATE
[patent_app_type] => utility
[patent_app_number] => 18/763040
[patent_app_country] => US
[patent_app_date] => 2024-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6539
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763040
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/763040 | MEMORY DEVICE WITH TUNABLE PROBABILISTIC STATE | Jul 2, 2024 | Pending |
Array
(
[id] => 20019302
[patent_doc_number] => 20250157524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-15
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/754855
[patent_app_country] => US
[patent_app_date] => 2024-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7635
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754855
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/754855 | SEMICONDUCTOR MEMORY DEVICE | Jun 25, 2024 | Pending |
Array
(
[id] => 20704021
[patent_doc_number] => 12626736
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-12
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/750232
[patent_app_country] => US
[patent_app_date] => 2024-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 20
[patent_no_of_words] => 4656
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750232
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/750232 | Semiconductor device | Jun 20, 2024 | Issued |
Array
(
[id] => 19893038
[patent_doc_number] => 20250118350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => APPARATUSES AND METHODS FOR MONITORED REFRESH MANAGEMENT OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/746618
[patent_app_country] => US
[patent_app_date] => 2024-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10049
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746618
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/746618 | Apparatuses and methods for monitored refresh management operations | Jun 17, 2024 | Issued |
Array
(
[id] => 19820742
[patent_doc_number] => 20250078949
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => APPARATUSES AND METHODS FOR HALF-PAGE MODES OF MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/745577
[patent_app_country] => US
[patent_app_date] => 2024-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22736
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745577
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/745577 | Apparatuses and methods for half-page modes of memory devices | Jun 16, 2024 | Issued |
Array
(
[id] => 20923799
[patent_doc_number] => 12718865
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-08-25
[patent_title] => Intra-package memory die communication structures
[patent_app_type] => utility
[patent_app_number] => 18/740242
[patent_app_country] => US
[patent_app_date] => 2024-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 9724
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740242
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/740242 | INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES | Jun 10, 2024 | Pending |
Array
(
[id] => 20666492
[patent_doc_number] => 12608267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-21
[patent_title] => Learned temperature compensation
[patent_app_type] => utility
[patent_app_number] => 18/737831
[patent_app_country] => US
[patent_app_date] => 2024-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 11026
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737831
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/737831 | Learned temperature compensation | Jun 6, 2024 | Issued |
Array
(
[id] => 20409765
[patent_doc_number] => 20250378874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-11
[patent_title] => Memory Cell Noise Protection via Bidirectional Threshold Switching Devices
[patent_app_type] => utility
[patent_app_number] => 18/735138
[patent_app_country] => US
[patent_app_date] => 2024-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6256
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735138
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/735138 | Memory Cell Noise Protection via Bidirectional Threshold Switching Devices | Jun 4, 2024 | Issued |
Array
(
[id] => 20063097
[patent_doc_number] => 20250201319
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => OPERATING METHOD OF MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/733182
[patent_app_country] => US
[patent_app_date] => 2024-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8468
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733182
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/733182 | Operating method of memory device | Jun 3, 2024 | Issued |
Array
(
[id] => 20399036
[patent_doc_number] => 20250374511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-04
[patent_title] => MEMORY WITH BITCELL-TO-PERIPHERY INTERFACE TAP CELL
[patent_app_type] => utility
[patent_app_number] => 18/680474
[patent_app_country] => US
[patent_app_date] => 2024-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680474
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/680474 | MEMORY WITH BITCELL-TO-PERIPHERY INTERFACE TAP CELL | May 30, 2024 | Issued |
Array
(
[id] => 19467685
[patent_doc_number] => 20240321355
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => PROGRAM CURRENT CONTROLLER AND SENSE CIRCUIT FOR CROSS-POINT MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/678802
[patent_app_country] => US
[patent_app_date] => 2024-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8967
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678802
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/678802 | PROGRAM CURRENT CONTROLLER AND SENSE CIRCUIT FOR CROSS-POINT MEMORY DEVICES | May 29, 2024 | Pending |