Search

Michael Thanh Tran

Examiner (ID: 149, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818
Total Applications
3177
Issued Applications
2960
Pending Applications
145
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19603297 [patent_doc_number] => 20240394177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS [patent_app_type] => utility [patent_app_number] => 18/675127 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 666 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675127
MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS May 26, 2024 Pending
Array ( [id] => 20923806 [patent_doc_number] => 12718872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => SRAM structure with asymmetric interconnection [patent_app_type] => utility [patent_app_number] => 18/672090 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 4543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672090 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672090
SRAM STRUCTURE WITH ASYMMETRIC INTERCONNECTION May 22, 2024 Pending
Array ( [id] => 19452369 [patent_doc_number] => 20240312499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => DIE LOCATION DETECTION FOR GROUPED MEMORY DIES [patent_app_type] => utility [patent_app_number] => 18/672339 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672339
DIE LOCATION DETECTION FOR GROUPED MEMORY DIES May 22, 2024 Pending
Array ( [id] => 20581191 [patent_doc_number] => 12573445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/670780 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670780
Memory device May 21, 2024 Issued
Array ( [id] => 20305193 [patent_doc_number] => 12451189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Partial block handling protocol in a non-volatile memory device [patent_app_type] => utility [patent_app_number] => 18/670073 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670073
Partial block handling protocol in a non-volatile memory device May 20, 2024 Issued
Array ( [id] => 19589387 [patent_doc_number] => 20240386944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => MEMORY DEVICE USING SEMICONDUCTOR ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/662248 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 533 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662248 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662248
MEMORY DEVICE USING SEMICONDUCTOR ELEMENTS May 12, 2024 Pending
Array ( [id] => 20530166 [patent_doc_number] => 12548607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Dynamic control of data transient rise time based on process, temperature, voltage (PVT) data in a memory device [patent_app_type] => utility [patent_app_number] => 18/653596 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3873 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653596 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653596
Dynamic control of data transient rise time based on process, temperature, voltage (PVT) data in a memory device May 1, 2024 Issued
Array ( [id] => 19633000 [patent_doc_number] => 20240411449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => MANAGING PROGRAMMING OPERATION SEQUENCE IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/646266 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646266
MANAGING PROGRAMMING OPERATION SEQUENCE IN A MEMORY SUB-SYSTEM Apr 24, 2024 Pending
Array ( [id] => 19974099 [patent_doc_number] => 12342734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Phase-change memory [patent_app_type] => utility [patent_app_number] => 18/646334 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646334 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646334
Phase-change memory Apr 24, 2024 Issued
Array ( [id] => 20404285 [patent_doc_number] => 12494265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => On-access error correction for content-addressable memory [patent_app_type] => utility [patent_app_number] => 18/645939 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645939
On-access error correction for content-addressable memory Apr 24, 2024 Issued
Array ( [id] => 19559618 [patent_doc_number] => 20240371410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => APPARATUS INCLUDING MULTIPLE HIGH BANDWIDTH MEMORY CUBES [patent_app_type] => utility [patent_app_number] => 18/642796 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642796 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642796
Apparatus including multiple high bandwidth memory cubes Apr 21, 2024 Issued
Array ( [id] => 20792691 [patent_doc_number] => 12666623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Semiconductor device and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 18/641435 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 2401 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641435 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641435
Semiconductor device and method of manufacturing semiconductor device Apr 21, 2024 Issued
Array ( [id] => 19618912 [patent_doc_number] => 20240404592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => PROGRAMMABLE INTERPOSERS FOR ELECTRICALLY CONNECTING INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/640569 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640569
PROGRAMMABLE INTERPOSERS FOR ELECTRICALLY CONNECTING INTEGRATED CIRCUITS Apr 18, 2024 Abandoned
Array ( [id] => 20235521 [patent_doc_number] => 20250292840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => METHOD FOR CORRUPTING DATA STORED IN A MEMORY, AND CORRESPONDING INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/635767 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635767
Method for corrupting data stored in a memory, and corresponding integrated circuit Apr 14, 2024 Issued
Array ( [id] => 19348877 [patent_doc_number] => 20240257841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => DYNAMIC ALLOCATION OF A CAPACITIVE COMPONENT IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/634074 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634074 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634074
Dynamic allocation of a capacitive component in a memory device Apr 11, 2024 Issued
Array ( [id] => 20111282 [patent_doc_number] => 12362017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Memory device with reduced area [patent_app_type] => utility [patent_app_number] => 18/632856 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632856
Memory device with reduced area Apr 10, 2024 Issued
Array ( [id] => 20332585 [patent_doc_number] => 12462869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Memory structure, manufacturing method thereof, operating method thereof, and memory array [patent_app_type] => utility [patent_app_number] => 18/619416 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619416 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619416
Memory structure, manufacturing method thereof, operating method thereof, and memory array Mar 27, 2024 Issued
Array ( [id] => 20146612 [patent_doc_number] => 12380958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor memory structure [patent_app_type] => utility [patent_app_number] => 18/614180 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614180
Semiconductor memory structure Mar 21, 2024 Issued
Array ( [id] => 19305201 [patent_doc_number] => 20240233781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => METHOD AND APPARATUS FOR POWER SAVING IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/610880 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610880
Method and apparatus for power saving in semiconductor devices Mar 19, 2024 Issued
Array ( [id] => 19283678 [patent_doc_number] => 20240220154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => ARRAY OF NON-VOLATILE MEMORY CELLS TO STORE DATA IN ANALOG FORM AND DIGITAL FORM [patent_app_type] => utility [patent_app_number] => 18/604884 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604884
Array of non-volatile memory cells to store data in analog form and digital form Mar 13, 2024 Issued
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