Search

Michael Thanh Tran

Examiner (ID: 3826, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2511
Total Applications
3148
Issued Applications
2945
Pending Applications
134
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19964632 [patent_doc_number] => 12334147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => First fire operation for ovonic threshold switch selector [patent_app_type] => utility [patent_app_number] => 18/581340 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581340
First fire operation for ovonic threshold switch selector Feb 18, 2024 Issued
Array ( [id] => 19926010 [patent_doc_number] => 12300302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Nonvolatile memory devices [patent_app_type] => utility [patent_app_number] => 18/581018 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 15970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581018
Nonvolatile memory devices Feb 18, 2024 Issued
Array ( [id] => 19850396 [patent_doc_number] => 20250095747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/428275 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428275
Memory device and operating method of the memory device Jan 30, 2024 Issued
Array ( [id] => 20044589 [patent_doc_number] => 20250182811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => OFFSET CALIBRATION METHOD AND APPARATUS FOR HIGH BANDWIDTH MEMORY 3 (HBM3) [patent_app_type] => utility [patent_app_number] => 18/423817 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423817
Offset calibration method and apparatus for high bandwidth memory 3 (HBM3) Jan 25, 2024 Issued
Array ( [id] => 20469231 [patent_doc_number] => 12525273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Memory devices including mechanism of protecting a vulnerable word line based on the previous refreshed word lines and relevant methods [patent_app_type] => utility [patent_app_number] => 18/413454 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11325 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413454
Memory devices including mechanism of protecting a vulnerable word line based on the previous refreshed word lines and relevant methods Jan 15, 2024 Issued
Array ( [id] => 19796029 [patent_doc_number] => 12236994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Semiconductor memory device and memory system having the same [patent_app_type] => utility [patent_app_number] => 18/413924 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413924
Semiconductor memory device and memory system having the same Jan 15, 2024 Issued
Array ( [id] => 20146592 [patent_doc_number] => 12380938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Memory device, semiconductor device, and electronic device [patent_app_type] => utility [patent_app_number] => 18/409150 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 64 [patent_no_of_words] => 38561 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409150 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409150
Memory device, semiconductor device, and electronic device Jan 9, 2024 Issued
Array ( [id] => 19347193 [patent_doc_number] => 20240256156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SENSE AMPLIFIERS AS STATIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/402990 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402990
Sense amplifiers as static random access memory Jan 2, 2024 Issued
Array ( [id] => 20088553 [patent_doc_number] => 20250218489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY DEVICES INCLUDING MECHANISM OF PROTECTING A VULNERABLE WORD LINE BASED ON THE PREVIOUS REFRESHED WORD LINES AND RELEVANT METHODS [patent_app_type] => utility [patent_app_number] => 18/401758 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401758
Memory devices including mechanism of protecting a vulnerable word line based on the previous refreshed word lines and relevant methods Jan 1, 2024 Issued
Array ( [id] => 19118497 [patent_doc_number] => 20240130247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => MAGNETIZATION ROTATIONAL ELEMENT AND MAGNETORESISTIVE EFFECT ELEMENT [patent_app_type] => utility [patent_app_number] => 18/397344 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397344
MAGNETIZATION ROTATIONAL ELEMENT AND MAGNETORESISTIVE EFFECT ELEMENT Dec 26, 2023 Pending
Array ( [id] => 20389123 [patent_doc_number] => 12488856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Memory device, operation method of memory device, and operation method of test device configured to test memory device [patent_app_type] => utility [patent_app_number] => 18/395010 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 10606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395010
Memory device, operation method of memory device, and operation method of test device configured to test memory device Dec 21, 2023 Issued
Array ( [id] => 20611010 [patent_doc_number] => 12586614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Data transmission/receiving circuit, data training circuit and semiconductor apparatus including the same [patent_app_type] => utility [patent_app_number] => 18/545860 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545860
Data transmission/receiving circuit, data training circuit and semiconductor apparatus including the same Dec 18, 2023 Issued
Array ( [id] => 19085938 [patent_doc_number] => 20240112739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => PROGRAMMING FOR THREE-DIMENSIONAL NAND MEMORY [patent_app_type] => utility [patent_app_number] => 18/537263 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537263
Programming for three-dimensional NAND memory Dec 11, 2023 Issued
Array ( [id] => 20266820 [patent_doc_number] => 12437816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Memory, a memory system, and a method for operating memory [patent_app_type] => utility [patent_app_number] => 18/528454 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8725 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528454
Memory, a memory system, and a method for operating memory Dec 3, 2023 Issued
Array ( [id] => 20036050 [patent_doc_number] => 20250174272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => GENERATING AND USING A STATE TRANSITION MATRIX FOR DECODING DATA IN A DNA-BASED STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/523202 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523202
Generating and using a state transition matrix for decoding data in a DNA-based storage system Nov 28, 2023 Issued
Array ( [id] => 20305182 [patent_doc_number] => 12451178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Synapse device and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/522109 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522109
Synapse device and method of operating the same Nov 27, 2023 Issued
Array ( [id] => 19879614 [patent_doc_number] => 20250111871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => MEMORY DEVICES HAVING A RANDOM NUMBER GENERATOR FOR PROTECTING MEMORY CELLS, AND METHODS FOR PROTECTING MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/515690 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515690 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515690
Memory devices having a random number generator for protecting memory cells, and methods for protecting memory devices Nov 20, 2023 Issued
Array ( [id] => 19252467 [patent_doc_number] => 20240203464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => METHODS FOR PROVIDING DEVICE STATUS IN RESPONSE TO READ COMMANDS DIRECTED TO WRITE-ONLY MODE REGISTER BITS AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 18/513317 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513317 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513317
Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same Nov 16, 2023 Issued
Array ( [id] => 20266807 [patent_doc_number] => 12437803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Buffer chip, semiconductor package including buffer chip and memory chip, operation method of buffer chip, and operation method of semiconductor package [patent_app_type] => utility [patent_app_number] => 18/509315 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4554 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509315 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/509315
Buffer chip, semiconductor package including buffer chip and memory chip, operation method of buffer chip, and operation method of semiconductor package Nov 14, 2023 Issued
Array ( [id] => 19023231 [patent_doc_number] => 20240079402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => MEMORY DEVICE WITH A MULTIPLEXED COMMAND/ADDRESS BUS [patent_app_type] => utility [patent_app_number] => 18/389113 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389113
Memory device with a multiplexed command/address bus Nov 12, 2023 Issued
Menu