Search

Michael Thanh Tran

Examiner (ID: 5527, Phone: (571)272-1795 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818
Total Applications
3128
Issued Applications
2940
Pending Applications
121
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19670665 [patent_doc_number] => 12183432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Shared decoder circuit and method [patent_app_type] => utility [patent_app_number] => 18/354445 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 15840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354445 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354445
Shared decoder circuit and method Jul 17, 2023 Issued
Array ( [id] => 20344747 [patent_doc_number] => 12468477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Semiconductor device for generating an internal voltage [patent_app_type] => utility [patent_app_number] => 18/351855 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7756 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351855 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351855
Semiconductor device for generating an internal voltage Jul 12, 2023 Issued
Array ( [id] => 19958427 [patent_doc_number] => 12328858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Silicon-on-insulator semiconductor device with a static random access memory circuit [patent_app_type] => utility [patent_app_number] => 18/347435 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347435 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347435
Silicon-on-insulator semiconductor device with a static random access memory circuit Jul 4, 2023 Issued
Array ( [id] => 18731528 [patent_doc_number] => 20230345848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/218570 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218570 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218570
Resistive random access memory and method of forming the same Jul 4, 2023 Issued
Array ( [id] => 20111274 [patent_doc_number] => 12362009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => SRAM performance optimization via transistor width and threshold voltage tuning [patent_app_type] => utility [patent_app_number] => 18/336304 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336304 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336304
SRAM performance optimization via transistor width and threshold voltage tuning Jun 15, 2023 Issued
Array ( [id] => 18712561 [patent_doc_number] => 20230335194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => 3D NAND FLASH AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/211163 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211163 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211163
3D NAND flash and operation method thereof Jun 15, 2023 Issued
Array ( [id] => 18712551 [patent_doc_number] => 20230335184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SRAM DEVICES WITH REDUCED COUPLING CAPACITANCE [patent_app_type] => utility [patent_app_number] => 18/336816 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336816 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336816
SRAM devices with reduced coupling capacitance Jun 15, 2023 Issued
Array ( [id] => 19679060 [patent_doc_number] => 12190931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Semiconductor memory devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 18/336386 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 41 [patent_no_of_words] => 17933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336386 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336386
Semiconductor memory devices and methods of manufacturing thereof Jun 15, 2023 Issued
Array ( [id] => 19159575 [patent_doc_number] => 20240152282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/335784 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335784 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/335784
Semiconductor memory device and operating method thereof Jun 14, 2023 Issued
Array ( [id] => 19906323 [patent_doc_number] => 12283335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Storage device suitable for high temperature [patent_app_type] => utility [patent_app_number] => 18/210099 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18210099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/210099
Storage device suitable for high temperature Jun 14, 2023 Issued
Array ( [id] => 18696091 [patent_doc_number] => 20230326522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 18/332058 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332058
Bit line and word line connection for memory array Jun 8, 2023 Issued
Array ( [id] => 19634334 [patent_doc_number] => 20240412783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => ANALOG IN-MEMORY DISCRETE SIGNAL PROCESSOR WITH MINIMUM USAGE OF ADC [patent_app_type] => utility [patent_app_number] => 18/332572 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332572
Analog in-memory discrete signal processor with minimum usage of ADC Jun 8, 2023 Issued
Array ( [id] => 19500118 [patent_doc_number] => 20240339136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => ROW DECODER AND ROW ADDRESS SCHEME IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/206488 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206488 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206488
Row decoder and row address scheme in a memory system Jun 5, 2023 Issued
Array ( [id] => 19926015 [patent_doc_number] => 12300307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Memory systems and methods for improved power management [patent_app_type] => utility [patent_app_number] => 18/203591 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 4359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203591 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203591
Memory systems and methods for improved power management May 29, 2023 Issued
Array ( [id] => 18655206 [patent_doc_number] => 20230301057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => MEMORY DEVICE INCLUDING PILLAR-SHAPED SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 18/322198 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322198 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322198
MEMORY DEVICE INCLUDING PILLAR-SHAPED SEMICONDUCTOR ELEMENT May 22, 2023 Abandoned
Array ( [id] => 19561862 [patent_doc_number] => 20240373654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => HYBRID MEMORY ON FRONT AND BACKSIDE OF A WAFER [patent_app_type] => utility [patent_app_number] => 18/312711 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312711
HYBRID MEMORY ON FRONT AND BACKSIDE OF A WAFER May 4, 2023 Pending
Array ( [id] => 19459954 [patent_doc_number] => 12100456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Memory device and erasing and verification method thereof [patent_app_type] => utility [patent_app_number] => 18/141207 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141207
Memory device and erasing and verification method thereof Apr 27, 2023 Issued
Array ( [id] => 18743091 [patent_doc_number] => 20230352079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/139374 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139374 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/139374
Semiconductor memory structure Apr 25, 2023 Issued
Array ( [id] => 19980036 [patent_doc_number] => 12347522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => On-chip automation of clock-to-Q access time measurement of a memory device [patent_app_type] => utility [patent_app_number] => 18/306584 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306584
On-chip automation of clock-to-Q access time measurement of a memory device Apr 24, 2023 Issued
Array ( [id] => 19193658 [patent_doc_number] => 20240172571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/305914 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305914 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305914
Semiconductor device and method of fabricating the same Apr 23, 2023 Issued
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