
Michael W. Chao
Examiner (ID: 3981)
| Most Active Art Unit | 2492 |
| Art Unit(s) | 2442, 2492 |
| Total Applications | 609 |
| Issued Applications | 384 |
| Pending Applications | 75 |
| Abandoned Applications | 167 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15234541
[patent_doc_number] => 10505001
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-10
[patent_title] => Semiconductor device and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 15/817779
[patent_app_country] => US
[patent_app_date] => 2017-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 6295
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817779
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/817779 | Semiconductor device and method of forming the same | Nov 19, 2017 | Issued |
Array
(
[id] => 14350377
[patent_doc_number] => 20190157161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-23
[patent_title] => MONOLITHIC CO-INTEGRATION OF MOSFET AND JFET FOR NEUROMORPHIC/COGNITIVE CIRCUIT APPLICATIONS
[patent_app_type] => utility
[patent_app_number] => 15/818674
[patent_app_country] => US
[patent_app_date] => 2017-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9690
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818674
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/818674 | Monolithic co-integration of MOSFET and JFET for neuromorphic/cognitive circuit applications | Nov 19, 2017 | Issued |
Array
(
[id] => 13610257
[patent_doc_number] => 20180356678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/817363
[patent_app_country] => US
[patent_app_date] => 2017-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10734
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817363
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/817363 | Display device | Nov 19, 2017 | Issued |
Array
(
[id] => 13378859
[patent_doc_number] => 20180240971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-23
[patent_title] => SELECTIVE DEPOSITION AND NITRIDIZATION OF BOTTOM ELECTRODE METAL FOR MRAM APPLICATIONS
[patent_app_type] => utility
[patent_app_number] => 15/805882
[patent_app_country] => US
[patent_app_date] => 2017-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8498
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15805882
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/805882 | Selective deposition and nitridization of bottom electrode metal for MRAM applications | Nov 6, 2017 | Issued |
Array
(
[id] => 14094321
[patent_doc_number] => 10243075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-26
[patent_title] => Junction FET semiconductor device with dummy mask structures for improved dimension control and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 15/802846
[patent_app_country] => US
[patent_app_date] => 2017-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4954
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802846
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/802846 | Junction FET semiconductor device with dummy mask structures for improved dimension control and method for forming the same | Nov 2, 2017 | Issued |
Array
(
[id] => 15200667
[patent_doc_number] => 10497840
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-03
[patent_title] => Wavelength-converting film and light emitting device and display device using the same
[patent_app_type] => utility
[patent_app_number] => 15/793026
[patent_app_country] => US
[patent_app_date] => 2017-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 7548
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793026
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/793026 | Wavelength-converting film and light emitting device and display device using the same | Oct 24, 2017 | Issued |
Array
(
[id] => 12223364
[patent_doc_number] => 20180061724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-01
[patent_title] => 'Method for Remapping a Packaged Extracted Die'
[patent_app_type] => utility
[patent_app_number] => 15/792351
[patent_app_country] => US
[patent_app_date] => 2017-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8615
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792351
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/792351 | Method for remapping a packaged extracted die | Oct 23, 2017 | Issued |
Array
(
[id] => 14558311
[patent_doc_number] => 10347626
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-09
[patent_title] => High quality deep trench oxide
[patent_app_type] => utility
[patent_app_number] => 15/790212
[patent_app_country] => US
[patent_app_date] => 2017-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 3185
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15790212
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/790212 | High quality deep trench oxide | Oct 22, 2017 | Issued |
Array
(
[id] => 13257205
[patent_doc_number] => 10141300
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-11-27
[patent_title] => Low capacitance transient voltage suppressor
[patent_app_type] => utility
[patent_app_number] => 15/788246
[patent_app_country] => US
[patent_app_date] => 2017-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 32
[patent_no_of_words] => 10175
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15788246
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/788246 | Low capacitance transient voltage suppressor | Oct 18, 2017 | Issued |
Array
(
[id] => 17971380
[patent_doc_number] => 11488929
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-01
[patent_title] => Bonding apparatus, bonding system, bonding method, and recording medium
[patent_app_type] => utility
[patent_app_number] => 16/347868
[patent_app_country] => US
[patent_app_date] => 2017-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 12076
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16347868
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/347868 | Bonding apparatus, bonding system, bonding method, and recording medium | Oct 10, 2017 | Issued |
Array
(
[id] => 12158613
[patent_doc_number] => 20180029879
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-01
[patent_title] => 'MEMS isolation structures'
[patent_app_type] => utility
[patent_app_number] => 15/728435
[patent_app_country] => US
[patent_app_date] => 2017-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 51
[patent_figures_cnt] => 51
[patent_no_of_words] => 14976
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728435
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/728435 | MEMS isolation structures | Oct 8, 2017 | Issued |
Array
(
[id] => 14460043
[patent_doc_number] => 10325996
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-18
[patent_title] => Method for producing a doped semiconductor layer
[patent_app_type] => utility
[patent_app_number] => 15/724604
[patent_app_country] => US
[patent_app_date] => 2017-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 30
[patent_no_of_words] => 12704
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724604
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/724604 | Method for producing a doped semiconductor layer | Oct 3, 2017 | Issued |
Array
(
[id] => 12141125
[patent_doc_number] => 20180019208
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-18
[patent_title] => 'Prototyping of Electronic Circuits with Edge Interconnects'
[patent_app_type] => utility
[patent_app_number] => 15/715963
[patent_app_country] => US
[patent_app_date] => 2017-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 6121
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715963
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/715963 | Prototyping of electronic circuits with edge interconnects | Sep 25, 2017 | Issued |
Array
(
[id] => 12669160
[patent_doc_number] => 20180114886
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-26
[patent_title] => ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/698783
[patent_app_country] => US
[patent_app_date] => 2017-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5973
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698783
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/698783 | Electronic device and method for fabricating the same | Sep 7, 2017 | Issued |
Array
(
[id] => 13451847
[patent_doc_number] => 20180277466
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-27
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/698926
[patent_app_country] => US
[patent_app_date] => 2017-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5879
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698926
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/698926 | Semiconductor device and method of manufacturing the same | Sep 7, 2017 | Issued |
Array
(
[id] => 12239994
[patent_doc_number] => 20180072857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-15
[patent_title] => 'Gas Barrier Coating For Semiconductor Nanoparticles'
[patent_app_type] => utility
[patent_app_number] => 15/699182
[patent_app_country] => US
[patent_app_date] => 2017-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2064
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699182
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/699182 | Gas Barrier Coating For Semiconductor Nanoparticles | Sep 7, 2017 | Abandoned |
Array
(
[id] => 13188149
[patent_doc_number] => 10109601
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-23
[patent_title] => Integrated circuit with detection of thinning via the back face and decoupling capacitors
[patent_app_type] => utility
[patent_app_number] => 15/698882
[patent_app_country] => US
[patent_app_date] => 2017-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4426
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698882
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/698882 | Integrated circuit with detection of thinning via the back face and decoupling capacitors | Sep 7, 2017 | Issued |
Array
(
[id] => 15061843
[patent_doc_number] => 10461234
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-29
[patent_title] => Metal-base substrate, semiconductor device and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 15/699289
[patent_app_country] => US
[patent_app_date] => 2017-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 34
[patent_no_of_words] => 10765
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699289
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/699289 | Metal-base substrate, semiconductor device and method for manufacturing the same | Sep 7, 2017 | Issued |
Array
(
[id] => 12651060
[patent_doc_number] => 20180108851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-19
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/698739
[patent_app_country] => US
[patent_app_date] => 2017-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12885
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698739
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/698739 | Display device | Sep 7, 2017 | Issued |
Array
(
[id] => 15250491
[patent_doc_number] => 10510775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-17
[patent_title] => Semiconductor device and manufacturing method of the same
[patent_app_type] => utility
[patent_app_number] => 15/695410
[patent_app_country] => US
[patent_app_date] => 2017-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 13707
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 351
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695410
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/695410 | Semiconductor device and manufacturing method of the same | Sep 4, 2017 | Issued |