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Michael Whitfield

Examiner (ID: 8144)

Most Active Art Unit
2312
Art Unit(s)
2312, 2309, 2303, 2784, 2305
Total Applications
331
Issued Applications
243
Pending Applications
2
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
07/460485 DUAL PORT MULTIPLE BLOCK MEMORY CAPABLE OF TIME DIVISIONAL OPERATION Jan 2, 1990 Abandoned
07/458985 DUAL PORT STATIC MEMORY WITH ONE CYCLE READ-MODIFY-WRITE OPERATION Dec 28, 1989 Abandoned
07/469885 SIGNAL MARGIN TESTING SYSTEM Dec 27, 1989 Abandoned
Array ( [id] => 2799235 [patent_doc_number] => 05155825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Page address translation cache replacement algorithm with improved testability' [patent_app_type] => 1 [patent_app_number] => 7/457464 [patent_app_country] => US [patent_app_date] => 1989-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4233 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155825.pdf [firstpage_image] =>[orig_patent_app_number] => 457464 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/457464
Page address translation cache replacement algorithm with improved testability Dec 26, 1989 Issued
Array ( [id] => 2803880 [patent_doc_number] => 05136700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'Apparatus and method for reducing interference in two-level cache memories' [patent_app_type] => 1 [patent_app_number] => 7/454922 [patent_app_country] => US [patent_app_date] => 1989-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6144 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/136/05136700.pdf [firstpage_image] =>[orig_patent_app_number] => 454922 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/454922
Apparatus and method for reducing interference in two-level cache memories Dec 21, 1989 Issued
07/456187 HIGH PERFORMANCE COMPUTER PIPELINE Dec 14, 1989 Abandoned
07/449677 RESOURCE ACCESS SECURITY SYSTEM FOR CONTROLLING ACCESS TO RESOURCES OF A DATA PROCESSING SYSTEM Dec 11, 1989 Abandoned
Array ( [id] => 2988475 [patent_doc_number] => 05226133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Two-level translation look-aside buffer using partial addresses for enhanced speed' [patent_app_type] => 1 [patent_app_number] => 7/444594 [patent_app_country] => US [patent_app_date] => 1989-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4939 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226133.pdf [firstpage_image] =>[orig_patent_app_number] => 444594 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/444594
Two-level translation look-aside buffer using partial addresses for enhanced speed Nov 30, 1989 Issued
Array ( [id] => 2877713 [patent_doc_number] => 05097444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Tunnel EEPROM with overerase protection' [patent_app_type] => 1 [patent_app_number] => 7/443535 [patent_app_country] => US [patent_app_date] => 1989-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 2093 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/097/05097444.pdf [firstpage_image] =>[orig_patent_app_number] => 443535 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/443535
Tunnel EEPROM with overerase protection Nov 28, 1989 Issued
Array ( [id] => 2757111 [patent_doc_number] => 05016220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-14 [patent_title] => 'Semiconductor memory device with logic level responsive testing circuit and method therefor' [patent_app_type] => 1 [patent_app_number] => 7/441005 [patent_app_country] => US [patent_app_date] => 1989-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5079 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/016/05016220.pdf [firstpage_image] =>[orig_patent_app_number] => 441005 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/441005
Semiconductor memory device with logic level responsive testing circuit and method therefor Nov 26, 1989 Issued
Array ( [id] => 2946776 [patent_doc_number] => 05197140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Sliced addressing multi-processor and method of operation' [patent_app_type] => 1 [patent_app_number] => 7/437946 [patent_app_country] => US [patent_app_date] => 1989-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 64 [patent_no_of_words] => 36904 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197140.pdf [firstpage_image] =>[orig_patent_app_number] => 437946 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/437946
Sliced addressing multi-processor and method of operation Nov 16, 1989 Issued
Array ( [id] => 2785762 [patent_doc_number] => 05132932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Dynamic random access memory having a plurality of rated voltages as operation supply voltage and operating method thereof' [patent_app_type] => 1 [patent_app_number] => 7/437425 [patent_app_country] => US [patent_app_date] => 1989-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 11594 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132932.pdf [firstpage_image] =>[orig_patent_app_number] => 437425 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/437425
Dynamic random access memory having a plurality of rated voltages as operation supply voltage and operating method thereof Nov 15, 1989 Issued
07/436368 PARALLEL PROTECTION CHECKING IN AN ADDRESS TRANSLATION LOOK-ASIDE BUFFER Nov 13, 1989 Abandoned
Array ( [id] => 2734817 [patent_doc_number] => 05058062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Nonvolatile semiconductor memory circuit including a reliable sense amplifier' [patent_app_type] => 1 [patent_app_number] => 7/431845 [patent_app_country] => US [patent_app_date] => 1989-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3816 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/058/05058062.pdf [firstpage_image] =>[orig_patent_app_number] => 431845 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/431845
Nonvolatile semiconductor memory circuit including a reliable sense amplifier Nov 5, 1989 Issued
Array ( [id] => 2888870 [patent_doc_number] => 05185874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Address generator for high speed data averager' [patent_app_type] => 1 [patent_app_number] => 7/428534 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3288 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185874.pdf [firstpage_image] =>[orig_patent_app_number] => 428534 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/428534
Address generator for high speed data averager Oct 29, 1989 Issued
07/426545 HIGH SPEED READOUT CIRCUIT Oct 25, 1989 Abandoned
07/426618 STRUCTURE STORAGE MANAGEMENT IN A GRAPHICS DISPLAY DEVICE Oct 23, 1989 Abandoned
Array ( [id] => 2925246 [patent_doc_number] => 05237668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media' [patent_app_type] => 1 [patent_app_number] => 7/424797 [patent_app_country] => US [patent_app_date] => 1989-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14187 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237668.pdf [firstpage_image] =>[orig_patent_app_number] => 424797 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/424797
Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media Oct 19, 1989 Issued
Array ( [id] => 2678389 [patent_doc_number] => 04999810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-12 [patent_title] => 'Surface-enhanced raman optical data storage system' [patent_app_type] => 1 [patent_app_number] => 7/423995 [patent_app_country] => US [patent_app_date] => 1989-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2050 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/999/04999810.pdf [firstpage_image] =>[orig_patent_app_number] => 423995 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/423995
Surface-enhanced raman optical data storage system Oct 18, 1989 Issued
07/421496 GLOBAL ROTATION OF DATA IN SYNCHRONOUS VECTOR PROCESSOR Oct 12, 1989 Abandoned
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