Search

Michael Y. Mapa

Examiner (ID: 17829, Phone: (571)270-5540 , Office: P/2645 )

Most Active Art Unit
2645
Art Unit(s)
2617, 2645
Total Applications
899
Issued Applications
612
Pending Applications
89
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3944671 [patent_doc_number] => 05935204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'System for a multi-processor system wherein each processor transfers a data block from cache if a cache hit and from main memory only if cache miss' [patent_app_type] => 1 [patent_app_number] => 8/852026 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3630 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935204.pdf [firstpage_image] =>[orig_patent_app_number] => 852026 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852026
System for a multi-processor system wherein each processor transfers a data block from cache if a cache hit and from main memory only if cache miss May 5, 1997 Issued
Array ( [id] => 4049425 [patent_doc_number] => 05943505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'System for high speed data and command transfer over an interface where a non-maskable interrupt signal indicates either a write command or received data' [patent_app_type] => 1 [patent_app_number] => 8/840315 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 15120 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943505.pdf [firstpage_image] =>[orig_patent_app_number] => 840315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840315
System for high speed data and command transfer over an interface where a non-maskable interrupt signal indicates either a write command or received data Apr 10, 1997 Issued
Array ( [id] => 3930845 [patent_doc_number] => 06002989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'System for quality control where inspection frequency of inspection apparatus is reset to minimize expected total loss based on derived frequency function and loss value' [patent_app_type] => 1 [patent_app_number] => 8/831298 [patent_app_country] => US [patent_app_date] => 1997-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 6390 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002989.pdf [firstpage_image] =>[orig_patent_app_number] => 831298 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/831298
System for quality control where inspection frequency of inspection apparatus is reset to minimize expected total loss based on derived frequency function and loss value Mar 31, 1997 Issued
Array ( [id] => 4057043 [patent_doc_number] => 05996028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Communication apparatus containing plurality of identification codes and operable for specific user based on identification code and private information stored in detachable recording medium' [patent_app_type] => 1 [patent_app_number] => 8/825420 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6608 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996028.pdf [firstpage_image] =>[orig_patent_app_number] => 825420 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/825420
Communication apparatus containing plurality of identification codes and operable for specific user based on identification code and private information stored in detachable recording medium Mar 27, 1997 Issued
Array ( [id] => 4121250 [patent_doc_number] => 06023739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'System for information processing comprising plurality of processors where interconnection nodes insure priority access to corresponding addressable spaces and establish hierarchy of processor priority access' [patent_app_type] => 1 [patent_app_number] => 8/821499 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3289 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023739.pdf [firstpage_image] =>[orig_patent_app_number] => 821499 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/821499
System for information processing comprising plurality of processors where interconnection nodes insure priority access to corresponding addressable spaces and establish hierarchy of processor priority access Mar 20, 1997 Issued
Array ( [id] => 3961038 [patent_doc_number] => 05974474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'System for automatic hardware identification and configuration where instance values are unique within the computer system and resource requirement conflicts are resolved by modifying resource settings' [patent_app_type] => 1 [patent_app_number] => 8/816104 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 17748 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974474.pdf [firstpage_image] =>[orig_patent_app_number] => 816104 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816104
System for automatic hardware identification and configuration where instance values are unique within the computer system and resource requirement conflicts are resolved by modifying resource settings Mar 13, 1997 Issued
Array ( [id] => 3923800 [patent_doc_number] => 05938747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Hardware command block delivery queue for host adapters and other devices with onboard processors' [patent_app_type] => 1 [patent_app_number] => 8/816980 [patent_app_country] => US [patent_app_date] => 1997-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11186 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938747.pdf [firstpage_image] =>[orig_patent_app_number] => 816980 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816980
Hardware command block delivery queue for host adapters and other devices with onboard processors Mar 12, 1997 Issued
Array ( [id] => 4076647 [patent_doc_number] => 05896548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Data transferring system having foreground and background modes and upon detecting significant pattern of access in foreground mode to change background mode control parameters' [patent_app_type] => 1 [patent_app_number] => 8/807452 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7794 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896548.pdf [firstpage_image] =>[orig_patent_app_number] => 807452 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/807452
Data transferring system having foreground and background modes and upon detecting significant pattern of access in foreground mode to change background mode control parameters Feb 27, 1997 Issued
Array ( [id] => 4057435 [patent_doc_number] => 05909594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'System for communications where first priority data transfer is not disturbed by second priority data transfer and where allocated bandwidth is removed when process terminates abnormally' [patent_app_type] => 1 [patent_app_number] => 8/805991 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10516 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909594.pdf [firstpage_image] =>[orig_patent_app_number] => 805991 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805991
System for communications where first priority data transfer is not disturbed by second priority data transfer and where allocated bandwidth is removed when process terminates abnormally Feb 23, 1997 Issued
Array ( [id] => 4008616 [patent_doc_number] => 05920731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Single-housing electrical device self-configurable to connect to PCMCIA compliant or non-PCMCIA compliant host interfaces' [patent_app_type] => 1 [patent_app_number] => 8/804222 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7386 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920731.pdf [firstpage_image] =>[orig_patent_app_number] => 804222 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804222
Single-housing electrical device self-configurable to connect to PCMCIA compliant or non-PCMCIA compliant host interfaces Feb 20, 1997 Issued
Array ( [id] => 4015264 [patent_doc_number] => 05923902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'System for synchronizing a plurality of nodes to concurrently generate output signals by adjusting relative timelags based on a maximum estimated timelag' [patent_app_type] => 1 [patent_app_number] => 8/800969 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6224 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923902.pdf [firstpage_image] =>[orig_patent_app_number] => 800969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/800969
System for synchronizing a plurality of nodes to concurrently generate output signals by adjusting relative timelags based on a maximum estimated timelag Feb 18, 1997 Issued
Array ( [id] => 4114164 [patent_doc_number] => 06049831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'System for transmitting network-related information where requested network information is separately transmitted as definitions and display information' [patent_app_type] => 1 [patent_app_number] => 8/800907 [patent_app_country] => US [patent_app_date] => 1997-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4933 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049831.pdf [firstpage_image] =>[orig_patent_app_number] => 800907 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/800907
System for transmitting network-related information where requested network information is separately transmitted as definitions and display information Feb 12, 1997 Issued
Array ( [id] => 3973054 [patent_doc_number] => 05978865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted' [patent_app_type] => 1 [patent_app_number] => 8/775262 [patent_app_country] => US [patent_app_date] => 1997-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7758 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978865.pdf [firstpage_image] =>[orig_patent_app_number] => 775262 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775262
System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted Feb 3, 1997 Issued
Array ( [id] => 3939727 [patent_doc_number] => 05954802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'System for interfacing ISA compatible computer devices with non-ISA buses using secondary DMA controllers and glue logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/792608 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5808 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954802.pdf [firstpage_image] =>[orig_patent_app_number] => 792608 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792608
System for interfacing ISA compatible computer devices with non-ISA buses using secondary DMA controllers and glue logic circuit Jan 30, 1997 Issued
Array ( [id] => 3936143 [patent_doc_number] => 05915128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Serial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another register' [patent_app_type] => 1 [patent_app_number] => 8/789904 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9972 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915128.pdf [firstpage_image] =>[orig_patent_app_number] => 789904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789904
Serial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another register Jan 28, 1997 Issued
Array ( [id] => 4268923 [patent_doc_number] => 06138199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'System for data transfer in a ring topology comprising selectors to selectively bypass external devices or a downstream device based upon presence indications' [patent_app_type] => 1 [patent_app_number] => 8/787868 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 10895 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138199.pdf [firstpage_image] =>[orig_patent_app_number] => 787868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/787868
System for data transfer in a ring topology comprising selectors to selectively bypass external devices or a downstream device based upon presence indications Jan 22, 1997 Issued
Array ( [id] => 4036535 [patent_doc_number] => 05968140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'System for configuring a device where stored configuration information is asserted at a first time and external operational data is asserted at a second time' [patent_app_type] => 1 [patent_app_number] => 8/778304 [patent_app_country] => US [patent_app_date] => 1997-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968140.pdf [firstpage_image] =>[orig_patent_app_number] => 778304 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778304
System for configuring a device where stored configuration information is asserted at a first time and external operational data is asserted at a second time Jan 1, 1997 Issued
Array ( [id] => 3944108 [patent_doc_number] => 05878279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'HDLC integrated circuit using internal arbitration to prioritize access to a shared internal bus amongst a plurality of devices' [patent_app_type] => 1 [patent_app_number] => 8/690928 [patent_app_country] => US [patent_app_date] => 1996-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 11189 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878279.pdf [firstpage_image] =>[orig_patent_app_number] => 690928 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/690928
HDLC integrated circuit using internal arbitration to prioritize access to a shared internal bus amongst a plurality of devices Jul 31, 1996 Issued
Array ( [id] => 4042247 [patent_doc_number] => 05931921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'System for CD-ROM audio playback utilizing blocking of data writing, resuming writing responsive to detecting data in response to difference between desired address and present address' [patent_app_type] => 1 [patent_app_number] => 8/672796 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5064 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931921.pdf [firstpage_image] =>[orig_patent_app_number] => 672796 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672796
System for CD-ROM audio playback utilizing blocking of data writing, resuming writing responsive to detecting data in response to difference between desired address and present address Jun 27, 1996 Issued
Array ( [id] => 4036595 [patent_doc_number] => 05968144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'System for supporting DMA I/O device using PCI bus and PCI-PCI bridge comprising programmable DMA controller for request arbitration and storing data transfer information' [patent_app_type] => 1 [patent_app_number] => 8/673243 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3988 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968144.pdf [firstpage_image] =>[orig_patent_app_number] => 673243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673243
System for supporting DMA I/O device using PCI bus and PCI-PCI bridge comprising programmable DMA controller for request arbitration and storing data transfer information Jun 26, 1996 Issued
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