Search

Michele C. Flood

Examiner (ID: 18881)

Most Active Art Unit
1655
Art Unit(s)
1641, 1655, 1654, 1651
Total Applications
822
Issued Applications
375
Pending Applications
76
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8295143 [patent_doc_number] => 08222933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Low power digital phase lock loop circuit' [patent_app_type] => utility [patent_app_number] => 12/775527 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 11369 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12775527 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775527
Low power digital phase lock loop circuit May 6, 2010 Issued
Array ( [id] => 8283597 [patent_doc_number] => 08217705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Voltage switching in a memory device' [patent_app_type] => utility [patent_app_number] => 12/775131 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3539 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12775131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775131
Voltage switching in a memory device May 5, 2010 Issued
Array ( [id] => 8739055 [patent_doc_number] => 08410830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Injection locked frequency divider and associated methods' [patent_app_type] => utility [patent_app_number] => 12/770383 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3215 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12770383 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/770383
Injection locked frequency divider and associated methods Apr 28, 2010 Issued
Array ( [id] => 7571457 [patent_doc_number] => 20110267113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'FREQUENCY MULTIPLIER' [patent_app_type] => utility [patent_app_number] => 12/768768 [patent_app_country] => US [patent_app_date] => 2010-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2944 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20110267113.pdf [firstpage_image] =>[orig_patent_app_number] => 12768768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/768768
FREQUENCY MULTIPLIER Apr 27, 2010 Abandoned
Array ( [id] => 6539445 [patent_doc_number] => 20100271094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'Signal Alignment System' [patent_app_type] => utility [patent_app_number] => 12/768513 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9459 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20100271094.pdf [firstpage_image] =>[orig_patent_app_number] => 12768513 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/768513
Signal alignment system Apr 26, 2010 Issued
Array ( [id] => 8556033 [patent_doc_number] => 08330508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Phase-generation circuitry with duty-cycle correction and method for generating a multiphase signal' [patent_app_type] => utility [patent_app_number] => 12/766423 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4852 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12766423 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766423
Phase-generation circuitry with duty-cycle correction and method for generating a multiphase signal Apr 22, 2010 Issued
Array ( [id] => 8556036 [patent_doc_number] => 08330511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'PLL charge pump with reduced coupling to bias nodes' [patent_app_type] => utility [patent_app_number] => 12/763418 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12763418 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/763418
PLL charge pump with reduced coupling to bias nodes Apr 19, 2010 Issued
Array ( [id] => 8295154 [patent_doc_number] => 08222941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Phase selector' [patent_app_type] => utility [patent_app_number] => 12/759886 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4258 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12759886 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759886
Phase selector Apr 13, 2010 Issued
Array ( [id] => 7507543 [patent_doc_number] => 20110254605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'HIGH SPEED DUAL MODULUS PRESCALER' [patent_app_type] => utility [patent_app_number] => 12/759931 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2776 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20110254605.pdf [firstpage_image] =>[orig_patent_app_number] => 12759931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759931
HIGH SPEED DUAL MODULUS PRESCALER Apr 13, 2010 Abandoned
Array ( [id] => 9021230 [patent_doc_number] => 08531217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Fractional-N frequency synthesizer having reduced fractional switching noise' [patent_app_type] => utility [patent_app_number] => 12/798685 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4303 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12798685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/798685
Fractional-N frequency synthesizer having reduced fractional switching noise Apr 8, 2010 Issued
Array ( [id] => 8933404 [patent_doc_number] => 08493109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'System and method to control a power on reset signal' [patent_app_type] => utility [patent_app_number] => 12/752027 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14410 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12752027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/752027
System and method to control a power on reset signal Mar 30, 2010 Issued
Array ( [id] => 8329374 [patent_doc_number] => 08237472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Frequency multiplier device and method thereof' [patent_app_type] => utility [patent_app_number] => 12/730312 [patent_app_country] => US [patent_app_date] => 2010-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6828 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12730312 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/730312
Frequency multiplier device and method thereof Mar 23, 2010 Issued
Array ( [id] => 4614762 [patent_doc_number] => 07990206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Device for supplying temperature dependent negative voltage' [patent_app_type] => utility [patent_app_number] => 12/727018 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4546 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990206.pdf [firstpage_image] =>[orig_patent_app_number] => 12727018 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/727018
Device for supplying temperature dependent negative voltage Mar 17, 2010 Issued
Array ( [id] => 5990308 [patent_doc_number] => 20110012648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'SYSTEMS AND METHODS FOR REDUCING AVERAGE CURRENT CONSUMPTION IN A LOCAL OSCILLATOR PATH' [patent_app_type] => utility [patent_app_number] => 12/724337 [patent_app_country] => US [patent_app_date] => 2010-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7354 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20110012648.pdf [firstpage_image] =>[orig_patent_app_number] => 12724337 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/724337
Systems and methods for reducing average current consumption in a local oscillator path Mar 14, 2010 Issued
Array ( [id] => 7707372 [patent_doc_number] => 20120001669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'LOW-POWER DUAL-EDGE-TRIGGERED STORAGE CELL WITH SCAN TEST SUPPORT AND CLOCK GATING CIRCUIT THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/203792 [patent_app_country] => US [patent_app_date] => 2010-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 21549 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13203792 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/203792
Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor Mar 14, 2010 Issued
Array ( [id] => 8306566 [patent_doc_number] => 08228102 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-24 [patent_title] => 'Phase-locked loop architecture and clock distribution system' [patent_app_type] => utility [patent_app_number] => 12/717062 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12717062 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717062
Phase-locked loop architecture and clock distribution system Mar 2, 2010 Issued
Array ( [id] => 6084779 [patent_doc_number] => 20110215850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'METHOD FOR TRACKING DELAY LOCKED LOOP CLOCK' [patent_app_type] => utility [patent_app_number] => 12/717104 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4825 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20110215850.pdf [firstpage_image] =>[orig_patent_app_number] => 12717104 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717104
Method for tracking delay locked loop clock Mar 2, 2010 Issued
Array ( [id] => 6084758 [patent_doc_number] => 20110215842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'PROGRAMMABLE DIGITAL CLOCK SIGNAL FREQUENCY DIVIDER MODULE AND MODULAR DIVIDER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/715396 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20110215842.pdf [firstpage_image] =>[orig_patent_app_number] => 12715396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715396
Programmable digital clock signal frequency divider module and modular divider circuit Mar 1, 2010 Issued
Array ( [id] => 7763425 [patent_doc_number] => 20120032717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'POWER-ON RESET CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/255704 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4462 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20120032717.pdf [firstpage_image] =>[orig_patent_app_number] => 13255704 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/255704
Power-on reset circuit Feb 24, 2010 Issued
Array ( [id] => 8295142 [patent_doc_number] => 08222932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Phase-locked loop with switched phase detectors' [patent_app_type] => utility [patent_app_number] => 12/710595 [patent_app_country] => US [patent_app_date] => 2010-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4792 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12710595 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/710595
Phase-locked loop with switched phase detectors Feb 22, 2010 Issued
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