
Michele C. Flood
Examiner (ID: 18881)
| Most Active Art Unit | 1655 |
| Art Unit(s) | 1641, 1655, 1654, 1651 |
| Total Applications | 822 |
| Issued Applications | 375 |
| Pending Applications | 76 |
| Abandoned Applications | 371 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8923085
[patent_doc_number] => 08489028
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-16
[patent_title] => 'System and method to enable resource partitioning in wireless networks'
[patent_app_type] => utility
[patent_app_number] => 12/465413
[patent_app_country] => US
[patent_app_date] => 2009-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 27
[patent_no_of_words] => 13066
[patent_no_of_claims] => 73
[patent_no_of_ind_claims] => 18
[patent_words_short_claim] => 12
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12465413
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/465413 | System and method to enable resource partitioning in wireless networks | May 12, 2009 | Issued |
Array
(
[id] => 5489479
[patent_doc_number] => 20090290550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-26
[patent_title] => 'SYSTEM AND METHOD TO ENABLE RESOURCE PARTITIONING IN WIRELESS NETWORKS'
[patent_app_type] => utility
[patent_app_number] => 12/465422
[patent_app_country] => US
[patent_app_date] => 2009-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 13093
[patent_no_of_claims] => 70
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20090290550.pdf
[firstpage_image] =>[orig_patent_app_number] => 12465422
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/465422 | System and method to enable resource partitioning in wireless networks | May 12, 2009 | Issued |
Array
(
[id] => 6592677
[patent_doc_number] => 20100291867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-18
[patent_title] => 'WIRELESS INTERFACE TO PROGRAM PHASE-CHANGE MEMORIES'
[patent_app_type] => utility
[patent_app_number] => 12/465506
[patent_app_country] => US
[patent_app_date] => 2009-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1534
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0291/20100291867.pdf
[firstpage_image] =>[orig_patent_app_number] => 12465506
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/465506 | Wireless interface to program phase-change memories | May 12, 2009 | Issued |
Array
(
[id] => 7725766
[patent_doc_number] => 08099043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-17
[patent_title] => 'Transmit channel in wideband high frequency wireless system using multiple transmit antenna, and method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/464199
[patent_app_country] => US
[patent_app_date] => 2009-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4546
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/099/08099043.pdf
[firstpage_image] =>[orig_patent_app_number] => 12464199
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/464199 | Transmit channel in wideband high frequency wireless system using multiple transmit antenna, and method thereof | May 11, 2009 | Issued |
Array
(
[id] => 6490273
[patent_doc_number] => 20100285746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-11
[patent_title] => 'NEAR FIELD COUPLING DEVICES AND ASSOCIATED SYSTEMS AND METHODS'
[patent_app_type] => utility
[patent_app_number] => 12/463841
[patent_app_country] => US
[patent_app_date] => 2009-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10162
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0285/20100285746.pdf
[firstpage_image] =>[orig_patent_app_number] => 12463841
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/463841 | Near field coupling devices and associated systems and methods | May 10, 2009 | Issued |
Array
(
[id] => 8551341
[patent_doc_number] => 08326233
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-04
[patent_title] => 'Method and system for a configurable tuned MOS capacitor'
[patent_app_type] => utility
[patent_app_number] => 12/463707
[patent_app_country] => US
[patent_app_date] => 2009-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5921
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12463707
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/463707 | Method and system for a configurable tuned MOS capacitor | May 10, 2009 | Issued |
Array
(
[id] => 4626134
[patent_doc_number] => 08005442
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-23
[patent_title] => 'Wireless network connection system and method using injection locked oscillators'
[patent_app_type] => utility
[patent_app_number] => 12/463382
[patent_app_country] => US
[patent_app_date] => 2009-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1443
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/005/08005442.pdf
[firstpage_image] =>[orig_patent_app_number] => 12463382
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/463382 | Wireless network connection system and method using injection locked oscillators | May 8, 2009 | Issued |
Array
(
[id] => 5372090
[patent_doc_number] => 20090309650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-17
[patent_title] => 'Booster circuit'
[patent_app_type] => utility
[patent_app_number] => 12/453340
[patent_app_country] => US
[patent_app_date] => 2009-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7352
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0309/20090309650.pdf
[firstpage_image] =>[orig_patent_app_number] => 12453340
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/453340 | Booster circuit | May 6, 2009 | Abandoned |
Array
(
[id] => 6396499
[patent_doc_number] => 20100164608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'BANDGAP CIRCUIT AND TEMPERATURE SENSING CIRCUIT INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/429317
[patent_app_country] => US
[patent_app_date] => 2009-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3126
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20100164608.pdf
[firstpage_image] =>[orig_patent_app_number] => 12429317
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/429317 | BANDGAP CIRCUIT AND TEMPERATURE SENSING CIRCUIT INCLUDING THE SAME | Apr 23, 2009 | Abandoned |
Array
(
[id] => 4466297
[patent_doc_number] => 07936209
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-03
[patent_title] => 'I/O buffer with low voltage semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 12/428556
[patent_app_country] => US
[patent_app_date] => 2009-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4716
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 301
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/936/07936209.pdf
[firstpage_image] =>[orig_patent_app_number] => 12428556
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/428556 | I/O buffer with low voltage semiconductor devices | Apr 22, 2009 | Issued |
Array
(
[id] => 4512011
[patent_doc_number] => 07915934
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-29
[patent_title] => 'Delay locked loop circuit and operational method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/427028
[patent_app_country] => US
[patent_app_date] => 2009-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 8747
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/915/07915934.pdf
[firstpage_image] =>[orig_patent_app_number] => 12427028
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/427028 | Delay locked loop circuit and operational method thereof | Apr 20, 2009 | Issued |
Array
(
[id] => 6265383
[patent_doc_number] => 20100253406
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'APPARATUS AND METHOD FOR COMPENSATING FOR PROCESS, VOLTAGE, AND TEMPERATURE VARIATION OF THE TIME DELAY OF A DIGITAL DELAY LINE'
[patent_app_type] => utility
[patent_app_number] => 12/418981
[patent_app_country] => US
[patent_app_date] => 2009-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9841
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0253/20100253406.pdf
[firstpage_image] =>[orig_patent_app_number] => 12418981
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/418981 | Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line | Apr 5, 2009 | Issued |
Array
(
[id] => 6268640
[patent_doc_number] => 20100254506
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'Counter and Frequency Divider Thereof'
[patent_app_type] => utility
[patent_app_number] => 12/418714
[patent_app_country] => US
[patent_app_date] => 2009-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2442
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0254/20100254506.pdf
[firstpage_image] =>[orig_patent_app_number] => 12418714
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/418714 | Counter and Frequency divider thereof | Apr 5, 2009 | Issued |
Array
(
[id] => 6265358
[patent_doc_number] => 20100253398
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'Fully Differential Single-Stage Frequency Divider Having 50% Duty Cycle'
[patent_app_type] => utility
[patent_app_number] => 12/417676
[patent_app_country] => US
[patent_app_date] => 2009-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3183
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0253/20100253398.pdf
[firstpage_image] =>[orig_patent_app_number] => 12417676
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/417676 | Fully Differential Single-Stage Frequency Divider Having 50% Duty Cycle | Apr 2, 2009 | Abandoned |
Array
(
[id] => 6265357
[patent_doc_number] => 20100253397
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'FREQUENCY DIVIDER CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/416736
[patent_app_country] => US
[patent_app_date] => 2009-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5311
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0253/20100253397.pdf
[firstpage_image] =>[orig_patent_app_number] => 12416736
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/416736 | Frequency divider circuit | Mar 31, 2009 | Issued |
Array
(
[id] => 5353408
[patent_doc_number] => 20090184752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-23
[patent_title] => 'BIAS CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/411104
[patent_app_country] => US
[patent_app_date] => 2009-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8818
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0184/20090184752.pdf
[firstpage_image] =>[orig_patent_app_number] => 12411104
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/411104 | BIAS CIRCUIT | Mar 24, 2009 | Abandoned |
Array
(
[id] => 6437022
[patent_doc_number] => 20100188127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-29
[patent_title] => 'SIGNAL ADJUSTING SYSTEM AND SIGNAL ADJUSTING METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/407760
[patent_app_country] => US
[patent_app_date] => 2009-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4017
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20100188127.pdf
[firstpage_image] =>[orig_patent_app_number] => 12407760
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/407760 | Signal adjusting system and signal adjusting method | Mar 18, 2009 | Issued |
Array
(
[id] => 5365364
[patent_doc_number] => 20090302923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'TERMINATED INPUT BUFFER WITH OFFSET CANCELLATION CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/395674
[patent_app_country] => US
[patent_app_date] => 2009-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2607
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0302/20090302923.pdf
[firstpage_image] =>[orig_patent_app_number] => 12395674
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/395674 | TERMINATED INPUT BUFFER WITH OFFSET CANCELLATION CIRCUIT | Feb 28, 2009 | Abandoned |
Array
(
[id] => 5933482
[patent_doc_number] => 20110210784
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-01
[patent_title] => 'RF SWITCHING DEVICE AND METHOD THEREFOR'
[patent_app_type] => utility
[patent_app_number] => 12/934999
[patent_app_country] => US
[patent_app_date] => 2009-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2994
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20110210784.pdf
[firstpage_image] =>[orig_patent_app_number] => 12934999
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/934999 | RF switching device and method therefor | Feb 3, 2009 | Issued |
Array
(
[id] => 7541078
[patent_doc_number] => 08058924
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-11-15
[patent_title] => 'Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/361804
[patent_app_country] => US
[patent_app_date] => 2009-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5984
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/058/08058924.pdf
[firstpage_image] =>[orig_patent_app_number] => 12361804
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/361804 | Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device | Jan 28, 2009 | Issued |