Search

Michele C. Flood

Examiner (ID: 18881)

Most Active Art Unit
1655
Art Unit(s)
1641, 1655, 1654, 1651
Total Applications
822
Issued Applications
375
Pending Applications
76
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8470648 [patent_doc_number] => 08299830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/528144 [patent_app_country] => US [patent_app_date] => 2008-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 3615 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12528144 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/528144
Semiconductor device Jan 17, 2008 Issued
Array ( [id] => 5579113 [patent_doc_number] => 20090174459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'QUADRATURE RADIO FREQUENCY MIXER WITH LOW NOISE AND LOW CONVERSION LOSS' [patent_app_type] => utility [patent_app_number] => 11/970311 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6364 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20090174459.pdf [firstpage_image] =>[orig_patent_app_number] => 11970311 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970311
Quadrature radio frequency mixer with low noise and low conversion loss Jan 6, 2008 Issued
Array ( [id] => 5432834 [patent_doc_number] => 20090167420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'DESIGN STRUCTURE FOR REGULATING THRESHOLD VOLTAGE IN TRANSISTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 11/965787 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6777 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20090167420.pdf [firstpage_image] =>[orig_patent_app_number] => 11965787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965787
DESIGN STRUCTURE FOR REGULATING THRESHOLD VOLTAGE IN TRANSISTOR DEVICES Dec 27, 2007 Abandoned
Array ( [id] => 4877214 [patent_doc_number] => 20080150597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'APPARATUS AND METHODS FOR CONTROLLING DELAY USING A DELAY UNIT AND A PHASE LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 11/962429 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4964 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150597.pdf [firstpage_image] =>[orig_patent_app_number] => 11962429 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962429
APPARATUS AND METHODS FOR CONTROLLING DELAY USING A DELAY UNIT AND A PHASE LOCKED LOOP Dec 20, 2007 Abandoned
Array ( [id] => 4661434 [patent_doc_number] => 20080252341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'CLOCK SIGNAL DISTRIBUTION CIRCUIT AND INTERFACE APPARATUS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/962969 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2738 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20080252341.pdf [firstpage_image] =>[orig_patent_app_number] => 11962969 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962969
CLOCK SIGNAL DISTRIBUTION CIRCUIT AND INTERFACE APPARATUS USING THE SAME Dec 20, 2007 Abandoned
Array ( [id] => 5407865 [patent_doc_number] => 20090121763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'ADJUSTABLE DUTY CYCLE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/962689 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5348 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20090121763.pdf [firstpage_image] =>[orig_patent_app_number] => 11962689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962689
Adjustable duty cycle circuit Dec 20, 2007 Issued
Array ( [id] => 4877114 [patent_doc_number] => 20080150497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'POWER SUPPLY VOLTAGE RESET CIRCUIT AND RESET SIGNAL GENERATING METHOD' [patent_app_type] => utility [patent_app_number] => 11/960771 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6317 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150497.pdf [firstpage_image] =>[orig_patent_app_number] => 11960771 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960771
Power supply voltage reset circuit and reset signal generating method Dec 19, 2007 Issued
Array ( [id] => 174381 [patent_doc_number] => 07659761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Operation mode setting apparatus, semiconductor integrated circuit including the same, and method of controlling semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/961949 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4542 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/659/07659761.pdf [firstpage_image] =>[orig_patent_app_number] => 11961949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961949
Operation mode setting apparatus, semiconductor integrated circuit including the same, and method of controlling semiconductor integrated circuit Dec 19, 2007 Issued
Array ( [id] => 4837704 [patent_doc_number] => 20080278208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/962057 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5182 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20080278208.pdf [firstpage_image] =>[orig_patent_app_number] => 11962057 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962057
DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS Dec 19, 2007 Abandoned
Array ( [id] => 5395555 [patent_doc_number] => 20090315618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'CURRENT MIRROR CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/376133 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2473 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315618.pdf [firstpage_image] =>[orig_patent_app_number] => 12376133 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/376133
CURRENT MIRROR CIRCUIT Dec 16, 2007 Abandoned
Array ( [id] => 4953056 [patent_doc_number] => 20080186080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Device for supplying temperature dependent negative voltage' [patent_app_type] => utility [patent_app_number] => 12/000232 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4517 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20080186080.pdf [firstpage_image] =>[orig_patent_app_number] => 12000232 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000232
Device for supplying temperature dependent negative voltage Dec 10, 2007 Abandoned
Array ( [id] => 4877222 [patent_doc_number] => 20080150605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Clock Distribution Network Architecture with Clock Skew Management' [patent_app_type] => utility [patent_app_number] => 11/949673 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8854 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150605.pdf [firstpage_image] =>[orig_patent_app_number] => 11949673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949673
Clock distribution network architecture with clock skew management Dec 2, 2007 Issued
Array ( [id] => 271063 [patent_doc_number] => 07564300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'High voltage generator' [patent_app_type] => utility [patent_app_number] => 11/949661 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564300.pdf [firstpage_image] =>[orig_patent_app_number] => 11949661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949661
High voltage generator Dec 2, 2007 Issued
Array ( [id] => 197902 [patent_doc_number] => 07639057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-29 [patent_title] => 'Clock gater system' [patent_app_type] => utility [patent_app_number] => 11/949424 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6945 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639057.pdf [firstpage_image] =>[orig_patent_app_number] => 11949424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949424
Clock gater system Dec 2, 2007 Issued
Array ( [id] => 4473191 [patent_doc_number] => 07944261 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-17 [patent_title] => 'Method and apparatus for detecting clock loss' [patent_app_type] => utility [patent_app_number] => 11/999194 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4058 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944261.pdf [firstpage_image] =>[orig_patent_app_number] => 11999194 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/999194
Method and apparatus for detecting clock loss Dec 2, 2007 Issued
Array ( [id] => 5320482 [patent_doc_number] => 20090058472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'VOLTAGE COMPARATOR CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/947777 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 987 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20090058472.pdf [firstpage_image] =>[orig_patent_app_number] => 11947777 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947777
VOLTAGE COMPARATOR CIRCUIT Nov 29, 2007 Abandoned
Array ( [id] => 256904 [patent_doc_number] => 07576582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Low-power clock gating circuit' [patent_app_type] => utility [patent_app_number] => 11/945387 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3665 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/576/07576582.pdf [firstpage_image] =>[orig_patent_app_number] => 11945387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945387
Low-power clock gating circuit Nov 26, 2007 Issued
Array ( [id] => 55426 [patent_doc_number] => 07768320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-03 [patent_title] => 'Process variation tolerant sense amplifier flop design' [patent_app_type] => utility [patent_app_number] => 11/943455 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768320.pdf [firstpage_image] =>[orig_patent_app_number] => 11943455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943455
Process variation tolerant sense amplifier flop design Nov 19, 2007 Issued
Array ( [id] => 134334 [patent_doc_number] => 07696811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications' [patent_app_type] => utility [patent_app_number] => 11/941342 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7044 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696811.pdf [firstpage_image] =>[orig_patent_app_number] => 11941342 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/941342
Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications Nov 15, 2007 Issued
Array ( [id] => 170012 [patent_doc_number] => 07667529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Charge pump warm-up current reduction' [patent_app_type] => utility [patent_app_number] => 11/983079 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1869 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/667/07667529.pdf [firstpage_image] =>[orig_patent_app_number] => 11983079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/983079
Charge pump warm-up current reduction Nov 6, 2007 Issued
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