Michele C. Flood

Array ( [id] => 14996 [patent_doc_number] => 07804333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Input buffer circuit' [patent_app_type] => utility [patent_app_number] => 11/823180 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2624 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/804/07804333.pdf [firstpage_image] =>[orig_patent_app_number] => 11823180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5346704 [patent_doc_number] => 20090002065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Buffer circuit for reducing differential-mode phase noise and quadrature phase error' [patent_app_type] => utility [patent_app_number] => 11/823079 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20090002065.pdf [firstpage_image] =>[orig_patent_app_number] => 11823079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4649252 [patent_doc_number] => 20080036507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Differential signal transmission and reception circuit capable of reducing power consumption' [patent_app_type] => utility [patent_app_number] => 11/812744 [patent_app_country] => US [patent_app_date] => 2007-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4416 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20080036507.pdf [firstpage_image] =>[orig_patent_app_number] => 11812744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4801026 [patent_doc_number] => 20080012613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Low-voltage detection reset circuit' [patent_app_type] => utility [patent_app_number] => 11/812510 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2036 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20080012613.pdf [firstpage_image] =>[orig_patent_app_number] => 11812510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 587627 [patent_doc_number] => 07449922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-11 [patent_title] => 'Sensing circuitry and method of detecting a change in voltage on at least one input line' [patent_app_type] => utility [patent_app_number] => 11/812237 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7576 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/449/07449922.pdf [firstpage_image] =>[orig_patent_app_number] => 11812237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5026613 [patent_doc_number] => 20070268059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 11/749266 [patent_app_country] => US [patent_app_date] => 2007-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8369 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20070268059.pdf [firstpage_image] =>[orig_patent_app_number] => 11749266 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 370307 [patent_doc_number] => 07477082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Method and circuit for driving H-bridge that reduces switching noise' [patent_app_type] => utility [patent_app_number] => 11/749147 [patent_app_country] => US [patent_app_date] => 2007-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4497 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/477/07477082.pdf [firstpage_image] =>[orig_patent_app_number] => 11749147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4769295 [patent_doc_number] => 20080054953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'RSDS/LVDS Driving Circuits Suitable for Low Working Voltages' [patent_app_type] => utility [patent_app_number] => 11/746629 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054953.pdf [firstpage_image] =>[orig_patent_app_number] => 11746629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4837709 [patent_doc_number] => 20080278212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'DC OFFSET CANCELING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/745456 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1717 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20080278212.pdf [firstpage_image] =>[orig_patent_app_number] => 11745456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 327202 [patent_doc_number] => 07514978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Terminated input buffer with offset cancellation circuit' [patent_app_type] => utility [patent_app_number] => 11/744891 [patent_app_country] => US [patent_app_date] => 2007-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2582 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514978.pdf [firstpage_image] =>[orig_patent_app_number] => 11744891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4857120 [patent_doc_number] => 20080265970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'VOLTAGE LEVEL SHIFTER AND BUFFER USING SAME' [patent_app_type] => utility [patent_app_number] => 11/741383 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14494 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265970.pdf [firstpage_image] =>[orig_patent_app_number] => 11741383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 23758 [patent_doc_number] => 07800417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Method and apparatus for generating frequency divided signals' [patent_app_type] => utility [patent_app_number] => 11/740638 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 9706 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/800/07800417.pdf [firstpage_image] =>[orig_patent_app_number] => 11740638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 589216 [patent_doc_number] => 07446585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Programmable delay circuit' [patent_app_type] => utility [patent_app_number] => 11/738523 [patent_app_country] => US [patent_app_date] => 2007-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5125 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446585.pdf [firstpage_image] =>[orig_patent_app_number] => 11738523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4897341 [patent_doc_number] => 20080116954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'LEVEL SHIFTER WITH SPEEDY OPERATION' [patent_app_type] => utility [patent_app_number] => 11/733168 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3926 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20080116954.pdf [firstpage_image] =>[orig_patent_app_number] => 11733168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4686069 [patent_doc_number] => 20080030250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'FLIP-FLOP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/693146 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10717 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20080030250.pdf [firstpage_image] =>[orig_patent_app_number] => 11693146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4715977 [patent_doc_number] => 20080238499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'CUSTOMIZABLE POWER-ON RESET CIRCUIT BASED ON CRITICAL CIRCUIT COUNTERPARTS' [patent_app_type] => utility [patent_app_number] => 11/693612 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5924 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20080238499.pdf [firstpage_image] =>[orig_patent_app_number] => 11693612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4975223 [patent_doc_number] => 20070216453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Power-on reset signal generation circuit and method' [patent_app_type] => utility [patent_app_number] => 11/725031 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20070216453.pdf [firstpage_image] =>[orig_patent_app_number] => 11725031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4749761 [patent_doc_number] => 20080157832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Power-On-Reset Circuit' [patent_app_type] => utility [patent_app_number] => 11/685799 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3132 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157832.pdf [firstpage_image] =>[orig_patent_app_number] => 11685799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5129419 [patent_doc_number] => 20070205816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Phase-locked loop circuit, delay-locked loop circuit and method of tuning output frequencies of the same' [patent_app_type] => utility [patent_app_number] => 11/712034 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10353 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20070205816.pdf [firstpage_image] =>[orig_patent_app_number] => 11712034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 104248 [patent_doc_number] => 07724049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal' [patent_app_type] => utility [patent_app_number] => 11/712162 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4813 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724049.pdf [firstpage_image] =>[orig_patent_app_number] => 11712162 [rel_patent_id] =>[rel_patent_doc_number] =>)