Michele Yoder

Array ( [id] => 1279323 [patent_doc_number] => 06654833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Bus arbitration' [patent_app_type] => B1 [patent_app_number] => 09/363547 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2944 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654833.pdf [firstpage_image] =>[orig_patent_app_number] => 09363547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1423378 [patent_doc_number] => 06539447 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Interrupt control system' [patent_app_type] => B1 [patent_app_number] => 09/362365 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6079 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539447.pdf [firstpage_image] =>[orig_patent_app_number] => 09362365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1381259 [patent_doc_number] => 06574691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Apparatus and method for interfacing a non-sequential 486 interface burst interface to a sequential ASB interface' [patent_app_type] => B1 [patent_app_number] => 09/363694 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574691.pdf [firstpage_image] =>[orig_patent_app_number] => 09363694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1567234 [patent_doc_number] => 06438634 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Data processing system including apparatuses connected via a bidirectional bus to each other and data transfer method for use with the same' [patent_app_type] => B1 [patent_app_number] => 09/361172 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5550 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438634.pdf [firstpage_image] =>[orig_patent_app_number] => 09361172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6265299 [patent_doc_number] => 20020188794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'METHOD AND APPARATUS FOR REPEATING (EXTENDING) TRANSACTIONS ON A BUS WITHOUT CLOCK DELAY' [patent_app_type] => new [patent_app_number] => 09/361367 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4898 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188794.pdf [firstpage_image] =>[orig_patent_app_number] => 09361367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7638638 [patent_doc_number] => 06397283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method of automatically adjusting interrupt frequency' [patent_app_type] => B1 [patent_app_number] => 09/359978 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2310 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397283.pdf [firstpage_image] =>[orig_patent_app_number] => 09359978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431944 [patent_doc_number] => 06516418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Portable computer having universal serial bus ports controlled power supply and a method of the same' [patent_app_type] => B1 [patent_app_number] => 09/360115 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5948 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516418.pdf [firstpage_image] =>[orig_patent_app_number] => 09360115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1319263 [patent_doc_number] => 06618813 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method for suspending, resuming, and turning on a computer system without being affected by an abnormal power failure' [patent_app_type] => B1 [patent_app_number] => 09/350219 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5190 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618813.pdf [firstpage_image] =>[orig_patent_app_number] => 09350219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1513200 [patent_doc_number] => 06442636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Parallel bus system capable of expanding peripheral devices' [patent_app_type] => B1 [patent_app_number] => 09/350109 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1767 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442636.pdf [firstpage_image] =>[orig_patent_app_number] => 09350109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1573735 [patent_doc_number] => 06499079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Subordinate bridge structure for a point-to-point computer interconnection bus' [patent_app_type] => B1 [patent_app_number] => 09/349563 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 46 [patent_no_of_words] => 25264 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499079.pdf [firstpage_image] =>[orig_patent_app_number] => 09349563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1296954 [patent_doc_number] => 06633934 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Computer system having reduced cabling requirements' [patent_app_type] => B1 [patent_app_number] => 09/349691 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7882 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633934.pdf [firstpage_image] =>[orig_patent_app_number] => 09349691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1297012 [patent_doc_number] => 06633945 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Fully connected cache coherent multiprocessing systems' [patent_app_type] => B1 [patent_app_number] => 09/349641 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4417 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633945.pdf [firstpage_image] =>[orig_patent_app_number] => 09349641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1508979 [patent_doc_number] => 06467012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors' [patent_app_type] => B1 [patent_app_number] => 09/350031 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 11321 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467012.pdf [firstpage_image] =>[orig_patent_app_number] => 09350031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7642413 [patent_doc_number] => 06430633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method and apparatus for automatic activation of bus termination on a fast ethernet repeater stack' [patent_app_type] => B1 [patent_app_number] => 09/349639 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6240 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430633.pdf [firstpage_image] =>[orig_patent_app_number] => 09349639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1513402 [patent_doc_number] => 06442699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Power control method and apparatus therefor' [patent_app_type] => B1 [patent_app_number] => 09/349931 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 17108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442699.pdf [firstpage_image] =>[orig_patent_app_number] => 09349931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1430259 [patent_doc_number] => 06526464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Mechanism to expand address space of a serial bus' [patent_app_type] => B1 [patent_app_number] => 09/349422 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2019 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526464.pdf [firstpage_image] =>[orig_patent_app_number] => 09349422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1456877 [patent_doc_number] => 06457133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Automatic transaction apparatus' [patent_app_type] => B1 [patent_app_number] => 09/348070 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4434 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457133.pdf [firstpage_image] =>[orig_patent_app_number] => 09348070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462380 [patent_doc_number] => 06427181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method of and apparatus for processing information, and providing medium' [patent_app_type] => B1 [patent_app_number] => 09/339815 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3693 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427181.pdf [firstpage_image] =>[orig_patent_app_number] => 09339815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459977 [patent_doc_number] => 06463496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Interface for an I2C bus' [patent_app_type] => B1 [patent_app_number] => 09/339648 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1947 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463496.pdf [firstpage_image] =>[orig_patent_app_number] => 09339648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431844 [patent_doc_number] => 06516367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method and system for detecting bus device configuration changes' [patent_app_type] => B1 [patent_app_number] => 09/339707 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516367.pdf [firstpage_image] =>[orig_patent_app_number] => 09339707 [rel_patent_id] =>[rel_patent_doc_number] =>)