Search

Michelle F. Paguio Frising

Examiner (ID: 18931, Phone: (571)272-6224 , Office: P/1651 )

Most Active Art Unit
1651
Art Unit(s)
1651
Total Applications
651
Issued Applications
402
Pending Applications
73
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6134044 [patent_doc_number] => 20020078318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Programming network interface cards to perform system and network management functions' [patent_app_type] => new [patent_app_number] => 09/738581 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3597 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20020078318.pdf [firstpage_image] =>[orig_patent_app_number] => 09738581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738581
Programming network interface cards to perform system and network management functions Dec 17, 2000 Issued
Array ( [id] => 1248775 [patent_doc_number] => 06678757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Print data management system and method' [patent_app_type] => B1 [patent_app_number] => 09/646420 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3534 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678757.pdf [firstpage_image] =>[orig_patent_app_number] => 09646420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/646420
Print data management system and method Dec 11, 2000 Issued
Array ( [id] => 1415320 [patent_doc_number] => 06549960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Architecture and apparatus for implementing 100 MBPS and GBPS ethernet address' [patent_app_type] => B1 [patent_app_number] => 09/714643 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11114 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549960.pdf [firstpage_image] =>[orig_patent_app_number] => 09714643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/714643
Architecture and apparatus for implementing 100 MBPS and GBPS ethernet address Nov 15, 2000 Issued
Array ( [id] => 1602171 [patent_doc_number] => 06493773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Data validity measure for efficient implementation of first-in-first-out memories for multi-processor systems' [patent_app_type] => B1 [patent_app_number] => 09/713998 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5433 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493773.pdf [firstpage_image] =>[orig_patent_app_number] => 09713998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713998
Data validity measure for efficient implementation of first-in-first-out memories for multi-processor systems Nov 14, 2000 Issued
09/601809 Computer adapter card Oct 3, 2000 Abandoned
Array ( [id] => 1062196 [patent_doc_number] => 06854021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-08 [patent_title] => 'Communications between partitions within a logically partitioned computer' [patent_app_type] => utility [patent_app_number] => 09/677454 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4070 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/854/06854021.pdf [firstpage_image] =>[orig_patent_app_number] => 09677454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677454
Communications between partitions within a logically partitioned computer Oct 1, 2000 Issued
09/677423 Wireless JAVA device Oct 1, 2000 Abandoned
Array ( [id] => 1456638 [patent_doc_number] => 06457076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'System and method for modifying software residing on a client computer that has access to a network' [patent_app_type] => B1 [patent_app_number] => 09/661117 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 14023 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457076.pdf [firstpage_image] =>[orig_patent_app_number] => 09661117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661117
System and method for modifying software residing on a client computer that has access to a network Sep 12, 2000 Issued
Array ( [id] => 1539990 [patent_doc_number] => 06338104 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'System including single connector pin supporter having two separate plurality of connector pins with one set of pins contacting state designating portion of memory card indicating write prohibit state' [patent_app_type] => B1 [patent_app_number] => 09/658189 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4099 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338104.pdf [firstpage_image] =>[orig_patent_app_number] => 09658189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658189
System including single connector pin supporter having two separate plurality of connector pins with one set of pins contacting state designating portion of memory card indicating write prohibit state Sep 7, 2000 Issued
Array ( [id] => 1408830 [patent_doc_number] => 06557047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'External storage device and method of accessing same' [patent_app_type] => B1 [patent_app_number] => 09/644650 [patent_app_country] => US [patent_app_date] => 2000-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 17215 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557047.pdf [firstpage_image] =>[orig_patent_app_number] => 09644650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/644650
External storage device and method of accessing same Aug 23, 2000 Issued
Array ( [id] => 1394864 [patent_doc_number] => 06567863 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Programmable controller coupler' [patent_app_type] => B1 [patent_app_number] => 09/601320 [patent_app_country] => US [patent_app_date] => 2000-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 926 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567863.pdf [firstpage_image] =>[orig_patent_app_number] => 09601320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/601320
Programmable controller coupler Aug 6, 2000 Issued
Array ( [id] => 1116528 [patent_doc_number] => 06804726 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method and apparatus for controlling electrical devices in response to sensed conditions' [patent_app_type] => B1 [patent_app_number] => 09/628081 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 15289 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804726.pdf [firstpage_image] =>[orig_patent_app_number] => 09628081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628081
Method and apparatus for controlling electrical devices in response to sensed conditions Jul 27, 2000 Issued
Array ( [id] => 1539016 [patent_doc_number] => 06412023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'System for communicating status via first signal line in a period of time in which control signal via second line is not transmitted' [patent_app_type] => B1 [patent_app_number] => 09/626281 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412023.pdf [firstpage_image] =>[orig_patent_app_number] => 09626281 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626281
System for communicating status via first signal line in a period of time in which control signal via second line is not transmitted Jul 24, 2000 Issued
Array ( [id] => 1521631 [patent_doc_number] => 06502145 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Semiconductor memory with application of predetermined power line potentials' [patent_app_type] => B1 [patent_app_number] => 09/609934 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 11014 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502145.pdf [firstpage_image] =>[orig_patent_app_number] => 09609934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609934
Semiconductor memory with application of predetermined power line potentials Jun 29, 2000 Issued
Array ( [id] => 1360951 [patent_doc_number] => 06587899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Dynamic message interface' [patent_app_type] => B1 [patent_app_number] => 09/595396 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2948 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587899.pdf [firstpage_image] =>[orig_patent_app_number] => 09595396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595396
Dynamic message interface Jun 13, 2000 Issued
Array ( [id] => 1075110 [patent_doc_number] => 06839778 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Speed power efficient USB method' [patent_app_type] => utility [patent_app_number] => 09/590831 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1914 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839778.pdf [firstpage_image] =>[orig_patent_app_number] => 09590831 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/590831
Speed power efficient USB method Jun 8, 2000 Issued
Array ( [id] => 789428 [patent_doc_number] => 06988191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-17 [patent_title] => 'Method for the synchronized start-up of a numerical control' [patent_app_type] => utility [patent_app_number] => 09/980303 [patent_app_country] => US [patent_app_date] => 2000-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5839 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/988/06988191.pdf [firstpage_image] =>[orig_patent_app_number] => 09980303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/980303
Method for the synchronized start-up of a numerical control May 26, 2000 Issued
Array ( [id] => 1234156 [patent_doc_number] => 06697885 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Automated DMA engine for ATA control' [patent_app_type] => B1 [patent_app_number] => 09/576591 [patent_app_country] => US [patent_app_date] => 2000-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 13494 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697885.pdf [firstpage_image] =>[orig_patent_app_number] => 09576591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576591
Automated DMA engine for ATA control May 21, 2000 Issued
Array ( [id] => 1214247 [patent_doc_number] => 06714997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method and means for enhanced interpretive instruction execution for a new integrated communications adapter using a queued direct input-output device' [patent_app_type] => B1 [patent_app_number] => 09/573694 [patent_app_country] => US [patent_app_date] => 2000-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 13040 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714997.pdf [firstpage_image] =>[orig_patent_app_number] => 09573694 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573694
Method and means for enhanced interpretive instruction execution for a new integrated communications adapter using a queued direct input-output device May 18, 2000 Issued
Array ( [id] => 1248764 [patent_doc_number] => 06678751 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'System for setting frame and protocol for transmission in a UART device' [patent_app_type] => B1 [patent_app_number] => 09/569657 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4887 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678751.pdf [firstpage_image] =>[orig_patent_app_number] => 09569657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569657
System for setting frame and protocol for transmission in a UART device May 11, 2000 Issued
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