Search

Michelle F. Paguio Frising

Examiner (ID: 18931, Phone: (571)272-6224 , Office: P/1651 )

Most Active Art Unit
1651
Art Unit(s)
1651
Total Applications
651
Issued Applications
402
Pending Applications
73
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1474848 [patent_doc_number] => 06408347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Integrated multi-function adapters using standard interfaces through single a access point' [patent_app_type] => B1 [patent_app_number] => 09/209968 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3872 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408347.pdf [firstpage_image] =>[orig_patent_app_number] => 09209968 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209968
Integrated multi-function adapters using standard interfaces through single a access point Dec 9, 1998 Issued
Array ( [id] => 1567322 [patent_doc_number] => 06363439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/206515 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5917 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363439.pdf [firstpage_image] =>[orig_patent_app_number] => 09206515 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206515
System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system Dec 6, 1998 Issued
Array ( [id] => 4280282 [patent_doc_number] => 06260083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'System for Java data block transfers of unknown length for applets and applications by determining length of data in local buffer and passing length of data combined with data out of program' [patent_app_type] => 1 [patent_app_number] => 9/206070 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2862 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260083.pdf [firstpage_image] =>[orig_patent_app_number] => 206070 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206070
System for Java data block transfers of unknown length for applets and applications by determining length of data in local buffer and passing length of data combined with data out of program Dec 3, 1998 Issued
Array ( [id] => 4269865 [patent_doc_number] => 06223236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Hierarchical bus structure data processing apparatus and method with reduced data transfer volume' [patent_app_type] => 1 [patent_app_number] => 9/204076 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10180 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223236.pdf [firstpage_image] =>[orig_patent_app_number] => 204076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204076
Hierarchical bus structure data processing apparatus and method with reduced data transfer volume Dec 2, 1998 Issued
Array ( [id] => 4317405 [patent_doc_number] => 06182164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Minimizing cache overhead by storing data for communications between a peripheral device and a host system into separate locations in memory' [patent_app_type] => 1 [patent_app_number] => 9/204978 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182164.pdf [firstpage_image] =>[orig_patent_app_number] => 204978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204978
Minimizing cache overhead by storing data for communications between a peripheral device and a host system into separate locations in memory Dec 2, 1998 Issued
Array ( [id] => 4291877 [patent_doc_number] => 06247076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Data storing method and apparatus for storing data while effectively utilizing a small capacity of a memory' [patent_app_type] => 1 [patent_app_number] => 9/203901 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11650 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247076.pdf [firstpage_image] =>[orig_patent_app_number] => 203901 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/203901
Data storing method and apparatus for storing data while effectively utilizing a small capacity of a memory Dec 1, 1998 Issued
Array ( [id] => 4323531 [patent_doc_number] => 06189052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'On-chip i/o processor supporting different protocols having on-chip controller for reading and setting pins, starting timers, and generating interrupts at well defined points of time' [patent_app_type] => 1 [patent_app_number] => 9/204212 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7466 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189052.pdf [firstpage_image] =>[orig_patent_app_number] => 204212 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204212
On-chip i/o processor supporting different protocols having on-chip controller for reading and setting pins, starting timers, and generating interrupts at well defined points of time Dec 1, 1998 Issued
Array ( [id] => 4294301 [patent_doc_number] => 06324596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Providing device status during bus retry operations' [patent_app_type] => 1 [patent_app_number] => 9/201550 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2597 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324596.pdf [firstpage_image] =>[orig_patent_app_number] => 201550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/201550
Providing device status during bus retry operations Nov 29, 1998 Issued
Array ( [id] => 1584615 [patent_doc_number] => 06449664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Two dimensional direct memory access in image processing systems' [patent_app_type] => B1 [patent_app_number] => 09/192616 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449664.pdf [firstpage_image] =>[orig_patent_app_number] => 09192616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192616
Two dimensional direct memory access in image processing systems Nov 15, 1998 Issued
Array ( [id] => 1462373 [patent_doc_number] => 06427178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Software modem having a multi-task plug-in architecture' [patent_app_type] => B2 [patent_app_number] => 09/193066 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3264 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427178.pdf [firstpage_image] =>[orig_patent_app_number] => 09193066 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193066
Software modem having a multi-task plug-in architecture Nov 15, 1998 Issued
Array ( [id] => 1587274 [patent_doc_number] => 06425021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'System for transferring data packets of different context utilizing single interface and concurrently processing data packets of different contexts' [patent_app_type] => B1 [patent_app_number] => 09/192891 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4778 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425021.pdf [firstpage_image] =>[orig_patent_app_number] => 09192891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192891
System for transferring data packets of different context utilizing single interface and concurrently processing data packets of different contexts Nov 15, 1998 Issued
Array ( [id] => 4349270 [patent_doc_number] => 06321277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Separable in-line automatic terminator for use with a data processing system bus' [patent_app_type] => 1 [patent_app_number] => 9/193327 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3736 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321277.pdf [firstpage_image] =>[orig_patent_app_number] => 193327 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193327
Separable in-line automatic terminator for use with a data processing system bus Nov 15, 1998 Issued
Array ( [id] => 1595787 [patent_doc_number] => 06484215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'System having I/O module number assignment utilizing module number signal line having pair of inputs adapted for receiving module number signal and propagation of module number signal down stream' [patent_app_type] => B1 [patent_app_number] => 09/192962 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3351 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484215.pdf [firstpage_image] =>[orig_patent_app_number] => 09192962 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192962
System having I/O module number assignment utilizing module number signal line having pair of inputs adapted for receiving module number signal and propagation of module number signal down stream Nov 15, 1998 Issued
Array ( [id] => 4280226 [patent_doc_number] => 06260079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method and system for enhancing fibre channel loop resiliency for a mass storage enclosure by increasing component redundancy and using shunt elements and intelligent bypass management' [patent_app_type] => 1 [patent_app_number] => 9/192548 [patent_app_country] => US [patent_app_date] => 1998-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 14349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260079.pdf [firstpage_image] =>[orig_patent_app_number] => 192548 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192548
Method and system for enhancing fibre channel loop resiliency for a mass storage enclosure by increasing component redundancy and using shunt elements and intelligent bypass management Nov 14, 1998 Issued
Array ( [id] => 4426874 [patent_doc_number] => 06195715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Interrupt control for multiple programs communicating with a common interrupt by associating programs to GP registers, defining interrupt register, polling GP registers, and invoking callback routine associated with defined interrupt register' [patent_app_type] => 1 [patent_app_number] => 9/192169 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195715.pdf [firstpage_image] =>[orig_patent_app_number] => 192169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192169
Interrupt control for multiple programs communicating with a common interrupt by associating programs to GP registers, defining interrupt register, polling GP registers, and invoking callback routine associated with defined interrupt register Nov 12, 1998 Issued
Array ( [id] => 4403621 [patent_doc_number] => 06263381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Preconditioning system for facilitating switching between electronic devices using automatic peripheral connection button to download predetermined software/parameters and automatically activating microphone and plurality of speakers' [patent_app_type] => 1 [patent_app_number] => 9/191742 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2833 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263381.pdf [firstpage_image] =>[orig_patent_app_number] => 191742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191742
Preconditioning system for facilitating switching between electronic devices using automatic peripheral connection button to download predetermined software/parameters and automatically activating microphone and plurality of speakers Nov 12, 1998 Issued
Array ( [id] => 1604453 [patent_doc_number] => 06434639 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation' [patent_app_type] => B1 [patent_app_number] => 09/191923 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3517 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434639.pdf [firstpage_image] =>[orig_patent_app_number] => 09191923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191923
System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation Nov 12, 1998 Issued
Array ( [id] => 4269778 [patent_doc_number] => 06223231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method and apparatus for highly-available processing of I/O requests while application processing continues' [patent_app_type] => 1 [patent_app_number] => 9/190664 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3274 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223231.pdf [firstpage_image] =>[orig_patent_app_number] => 190664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190664
Method and apparatus for highly-available processing of I/O requests while application processing continues Nov 11, 1998 Issued
Array ( [id] => 4391366 [patent_doc_number] => 06289403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method and arrangement for controlling a data transmission' [patent_app_type] => 1 [patent_app_number] => 9/190357 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3964 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289403.pdf [firstpage_image] =>[orig_patent_app_number] => 190357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190357
Method and arrangement for controlling a data transmission Nov 11, 1998 Issued
Array ( [id] => 4380803 [patent_doc_number] => 06256682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Signaling of power modes over an interface bus' [patent_app_type] => 1 [patent_app_number] => 9/190379 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6100 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256682.pdf [firstpage_image] =>[orig_patent_app_number] => 190379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190379
Signaling of power modes over an interface bus Nov 9, 1998 Issued
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