Search

Michelle F. Paguio Frising

Examiner (ID: 18931, Phone: (571)272-6224 , Office: P/1651 )

Most Active Art Unit
1651
Art Unit(s)
1651
Total Applications
651
Issued Applications
402
Pending Applications
73
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4178610 [patent_doc_number] => 06115758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Slot control system with fixed sequence and dynamic slot effect utilizing slot processor for continuously detecting operation request signal and immediately allowing next port or block operation when no operation request signal' [patent_app_type] => 1 [patent_app_number] => 9/174323 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3520 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115758.pdf [firstpage_image] =>[orig_patent_app_number] => 174323 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174323
Slot control system with fixed sequence and dynamic slot effect utilizing slot processor for continuously detecting operation request signal and immediately allowing next port or block operation when no operation request signal Oct 18, 1998 Issued
Array ( [id] => 4309790 [patent_doc_number] => 06212580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Integrated recorder system which reads an instrumental signal from an input module so as to record instrumental data derived from the instrumental signal, and transmits the instrumental data recorded therein to an output module' [patent_app_type] => 1 [patent_app_number] => 9/170486 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4701 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212580.pdf [firstpage_image] =>[orig_patent_app_number] => 170486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170486
Integrated recorder system which reads an instrumental signal from an input module so as to record instrumental data derived from the instrumental signal, and transmits the instrumental data recorded therein to an output module Oct 12, 1998 Issued
Array ( [id] => 4280240 [patent_doc_number] => 06260080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'System for improving signal quality between CPU and floppy disk drive in notebook computer utilizing pull-up device disposed between terminals connected to control signals and one of power supply potentials' [patent_app_type] => 1 [patent_app_number] => 9/170110 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2102 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260080.pdf [firstpage_image] =>[orig_patent_app_number] => 170110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170110
System for improving signal quality between CPU and floppy disk drive in notebook computer utilizing pull-up device disposed between terminals connected to control signals and one of power supply potentials Oct 12, 1998 Issued
Array ( [id] => 1452226 [patent_doc_number] => 06370603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Configurable universal serial bus (USB) controller implemented on a single integrated circuit (IC) chip with media access control (MAC)' [patent_app_type] => B1 [patent_app_number] => 09/166501 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6096 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370603.pdf [firstpage_image] =>[orig_patent_app_number] => 09166501 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/166501
Configurable universal serial bus (USB) controller implemented on a single integrated circuit (IC) chip with media access control (MAC) Oct 4, 1998 Issued
Array ( [id] => 1438639 [patent_doc_number] => 06356962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Network device and method of controlling flow of data arranged in frames in a data-based network' [patent_app_type] => B1 [patent_app_number] => 09/163772 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 59 [patent_no_of_words] => 14403 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356962.pdf [firstpage_image] =>[orig_patent_app_number] => 09163772 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163772
Network device and method of controlling flow of data arranged in frames in a data-based network Sep 29, 1998 Issued
Array ( [id] => 4422165 [patent_doc_number] => 06173343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Data processing system and method with central processing unit-determined peripheral device service' [patent_app_type] => 1 [patent_app_number] => 9/156217 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2626 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173343.pdf [firstpage_image] =>[orig_patent_app_number] => 156217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156217
Data processing system and method with central processing unit-determined peripheral device service Sep 17, 1998 Issued
Array ( [id] => 1438644 [patent_doc_number] => 06356965 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Hotkey for network service boot' [patent_app_type] => B1 [patent_app_number] => 09/149336 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5218 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356965.pdf [firstpage_image] =>[orig_patent_app_number] => 09149336 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149336
Hotkey for network service boot Sep 7, 1998 Issued
Array ( [id] => 4317331 [patent_doc_number] => 06182160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method and system for using editor objects to connect components' [patent_app_type] => 1 [patent_app_number] => 9/148397 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5451 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182160.pdf [firstpage_image] =>[orig_patent_app_number] => 148397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/148397
Method and system for using editor objects to connect components Sep 3, 1998 Issued
Array ( [id] => 4311679 [patent_doc_number] => 06237028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Host central processor with associated controller to capture a selected one of a number of memory units via path control commands' [patent_app_type] => 1 [patent_app_number] => 9/152692 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2734 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237028.pdf [firstpage_image] =>[orig_patent_app_number] => 152692 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/152692
Host central processor with associated controller to capture a selected one of a number of memory units via path control commands Sep 1, 1998 Issued
Array ( [id] => 4161798 [patent_doc_number] => 06032196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'System for adding a new entry to a web page table upon receiving a web page including a link to another web page not having a corresponding entry in the web page table' [patent_app_type] => 1 [patent_app_number] => 9/143110 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6268 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032196.pdf [firstpage_image] =>[orig_patent_app_number] => 143110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143110
System for adding a new entry to a web page table upon receiving a web page including a link to another web page not having a corresponding entry in the web page table Aug 27, 1998 Issued
Array ( [id] => 4202240 [patent_doc_number] => 06094697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Information processing system including processing device for detecting non-conductivity of state-indicating non-conductive member and discriminating prohibit state of writing information to information writable storage medium' [patent_app_type] => 1 [patent_app_number] => 9/143739 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4009 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094697.pdf [firstpage_image] =>[orig_patent_app_number] => 143739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143739
Information processing system including processing device for detecting non-conductivity of state-indicating non-conductive member and discriminating prohibit state of writing information to information writable storage medium Aug 27, 1998 Issued
Array ( [id] => 4316009 [patent_doc_number] => 06199122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Computer system, external storage, converter system, and recording medium for converting a serial command and data standard to a parallel one' [patent_app_type] => 1 [patent_app_number] => 9/120326 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199122.pdf [firstpage_image] =>[orig_patent_app_number] => 120326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120326
Computer system, external storage, converter system, and recording medium for converting a serial command and data standard to a parallel one Jul 21, 1998 Issued
Array ( [id] => 4177282 [patent_doc_number] => 06108725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration to allow access to a common internal bus' [patent_app_type] => 1 [patent_app_number] => 9/110929 [patent_app_country] => US [patent_app_date] => 1998-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9173 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108725.pdf [firstpage_image] =>[orig_patent_app_number] => 110929 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110929
Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration to allow access to a common internal bus Jul 5, 1998 Issued
Array ( [id] => 4380832 [patent_doc_number] => 06256684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'System for transferring data in high speed between host computer and peripheral device utilizing peripheral interface with accelerated mode' [patent_app_type] => 1 [patent_app_number] => 9/103451 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3801 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256684.pdf [firstpage_image] =>[orig_patent_app_number] => 103451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103451
System for transferring data in high speed between host computer and peripheral device utilizing peripheral interface with accelerated mode Jun 23, 1998 Issued
Array ( [id] => 1484928 [patent_doc_number] => 06453377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Computer including optical interconnect, memory unit, and method of assembling a computer' [patent_app_type] => B1 [patent_app_number] => 09/098050 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3153 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453377.pdf [firstpage_image] =>[orig_patent_app_number] => 09098050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098050
Computer including optical interconnect, memory unit, and method of assembling a computer Jun 15, 1998 Issued
Array ( [id] => 4171297 [patent_doc_number] => 06125415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Transmission system having adjustable output signal levels utilizing transistors selectable between open and closed states in accordance with control input state' [patent_app_type] => 1 [patent_app_number] => 9/095180 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4584 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125415.pdf [firstpage_image] =>[orig_patent_app_number] => 095180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095180
Transmission system having adjustable output signal levels utilizing transistors selectable between open and closed states in accordance with control input state Jun 9, 1998 Issued
Array ( [id] => 4176412 [patent_doc_number] => 06157969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Device for connecting DMA request signals to a selected one of DMA input lines' [patent_app_type] => 1 [patent_app_number] => 9/091197 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1115 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157969.pdf [firstpage_image] =>[orig_patent_app_number] => 091197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/091197
Device for connecting DMA request signals to a selected one of DMA input lines Jun 9, 1998 Issued
Array ( [id] => 4203406 [patent_doc_number] => 06161152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'System for providing asynchronous I/O operations by identifying and polling a portal from an application process using a table of entries corresponding to I/O operations' [patent_app_type] => 1 [patent_app_number] => 9/090961 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161152.pdf [firstpage_image] =>[orig_patent_app_number] => 090961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090961
System for providing asynchronous I/O operations by identifying and polling a portal from an application process using a table of entries corresponding to I/O operations Jun 3, 1998 Issued
Array ( [id] => 4259969 [patent_doc_number] => 06167472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'System for communicating with and initializing a computer peripheral utilizing a masked value generated by exclusive-or of data and corresponding mask' [patent_app_type] => 1 [patent_app_number] => 9/087302 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5486 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167472.pdf [firstpage_image] =>[orig_patent_app_number] => 087302 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087302
System for communicating with and initializing a computer peripheral utilizing a masked value generated by exclusive-or of data and corresponding mask May 28, 1998 Issued
Array ( [id] => 4237077 [patent_doc_number] => 06112267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels' [patent_app_type] => 1 [patent_app_number] => 9/086134 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 8624 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112267.pdf [firstpage_image] =>[orig_patent_app_number] => 086134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086134
Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels May 27, 1998 Issued
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