Michelle F. Paguio Frising

Array ( [id] => 4049439 [patent_doc_number] => 05943506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'System for facilitating data I/O between serial bus input device and non-serial bus cognition application by generating alternate interrupt and shutting off interrupt triggering activities' [patent_app_type] => 1 [patent_app_number] => 8/622471 [patent_app_country] => US [patent_app_date] => 1996-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4435 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943506.pdf [firstpage_image] =>[orig_patent_app_number] => 622471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3803606 [patent_doc_number] => 05822616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'DMA controller with prefetch cache rechecking in response to memory fetch decision unit\'s instruction when address comparing unit determines input address and prefetch address coincide' [patent_app_type] => 1 [patent_app_number] => 8/618137 [patent_app_country] => US [patent_app_date] => 1996-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 7224 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822616.pdf [firstpage_image] =>[orig_patent_app_number] => 618137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4014272 [patent_doc_number] => 05906658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Message queuing on a data storage system utilizing message queuing in intended recipient\'s queue' [patent_app_type] => 1 [patent_app_number] => 8/616486 [patent_app_country] => US [patent_app_date] => 1996-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5260 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/906/05906658.pdf [firstpage_image] =>[orig_patent_app_number] => 616486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4008735 [patent_doc_number] => 05892969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method for concurrently executing a configured string of concurrent I/O command blocks within a chain to perform a raid 5 I/O operation' [patent_app_type] => 1 [patent_app_number] => 8/615479 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 27380 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892969.pdf [firstpage_image] =>[orig_patent_app_number] => 615479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3842392 [patent_doc_number] => 05784633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'System for obtaining status data unrelated to user data path from a modem and providing control data to the modem without interrupting user data flow' [patent_app_type] => 1 [patent_app_number] => 8/614461 [patent_app_country] => US [patent_app_date] => 1996-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7302 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784633.pdf [firstpage_image] =>[orig_patent_app_number] => 614461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3768581 [patent_doc_number] => 05721955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'System for transferring portion of data to host from buffer if size of packet is greater than first threshold value but less than second threshold value' [patent_app_type] => 1 [patent_app_number] => 8/603686 [patent_app_country] => US [patent_app_date] => 1996-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4658 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721955.pdf [firstpage_image] =>[orig_patent_app_number] => 603686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3850252 [patent_doc_number] => 05815732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'System for service activation programming of wireless network access devices using an external module' [patent_app_type] => 1 [patent_app_number] => 8/603465 [patent_app_country] => US [patent_app_date] => 1996-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2635 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815732.pdf [firstpage_image] =>[orig_patent_app_number] => 603465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4042282 [patent_doc_number] => 05931923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'System for accessing control to a peripheral device utilizing a synchronization primitive within the peripheral device' [patent_app_type] => 1 [patent_app_number] => 8/602199 [patent_app_country] => US [patent_app_date] => 1996-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3024 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931923.pdf [firstpage_image] =>[orig_patent_app_number] => 602199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3850267 [patent_doc_number] => 05815733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'System for handling interrupts in a computer system using asic reset input line coupled to set of status circuits for presetting values in the status circuits' [patent_app_type] => 1 [patent_app_number] => 8/595493 [patent_app_country] => US [patent_app_date] => 1996-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815733.pdf [firstpage_image] =>[orig_patent_app_number] => 595493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257059 [patent_doc_number] => 06145023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Information storage and information processing system utilizing state-designating member provided on supporting card surface which produces write-permitting or write-inhibiting signal' [patent_app_type] => 1 [patent_app_number] => 8/592508 [patent_app_country] => US [patent_app_date] => 1996-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4009 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145023.pdf [firstpage_image] =>[orig_patent_app_number] => 592508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4089471 [patent_doc_number] => 05966545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'System for interfacing network applications with different versions of a network protocol by providing base class at session level and invoking subclass from base class at session level' [patent_app_type] => 1 [patent_app_number] => 8/591858 [patent_app_country] => US [patent_app_date] => 1996-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2945 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966545.pdf [firstpage_image] =>[orig_patent_app_number] => 591858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3841009 [patent_doc_number] => 05784541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'System for controlling multiple controllable devices according to a script transmitted from a personal computer' [patent_app_type] => 1 [patent_app_number] => 8/588473 [patent_app_country] => US [patent_app_date] => 1996-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 9028 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 587 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784541.pdf [firstpage_image] =>[orig_patent_app_number] => 588473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4023242 [patent_doc_number] => 05889959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Fast write initialization method and system for loading channel adapter microcode' [patent_app_type] => 1 [patent_app_number] => 8/583376 [patent_app_country] => US [patent_app_date] => 1996-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6189 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889959.pdf [firstpage_image] =>[orig_patent_app_number] => 583376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3895309 [patent_doc_number] => 05799209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration' [patent_app_type] => 1 [patent_app_number] => 8/581467 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 8841 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799209.pdf [firstpage_image] =>[orig_patent_app_number] => 581467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4017921 [patent_doc_number] => 05859990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'System for transferring data segments from a first storage device to a second storage device using an alignment stage including even and odd temporary devices' [patent_app_type] => 1 [patent_app_number] => 8/581494 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10071 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859990.pdf [firstpage_image] =>[orig_patent_app_number] => 581494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3803131 [patent_doc_number] => 05737571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'System for discriminating that an external processor is permitted to access a data storage device utilizing prescribed control signals including access enable signal' [patent_app_type] => 1 [patent_app_number] => 8/581497 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7936 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737571.pdf [firstpage_image] =>[orig_patent_app_number] => 581497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3871910 [patent_doc_number] => 05768530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'High speed integrated circuit interface for fibre channel communications' [patent_app_type] => 1 [patent_app_number] => 8/580508 [patent_app_country] => US [patent_app_date] => 1995-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 11566 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768530.pdf [firstpage_image] =>[orig_patent_app_number] => 580508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3893971 [patent_doc_number] => 05826004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Input/output device with self-test capability in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/574478 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4736 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/826/05826004.pdf [firstpage_image] =>[orig_patent_app_number] => 574478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873391 [patent_doc_number] => 05768627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'External parallel-port device using a timer to measure and adjust data transfer rate' [patent_app_type] => 1 [patent_app_number] => 8/573497 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7132 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768627.pdf [firstpage_image] =>[orig_patent_app_number] => 573497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960716 [patent_doc_number] => 05974455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'System for adding new entry to web page table upon receiving web page including link to another web page not having corresponding entry in web page table' [patent_app_type] => 1 [patent_app_number] => 8/571748 [patent_app_country] => US [patent_app_date] => 1995-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6267 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974455.pdf [firstpage_image] =>[orig_patent_app_number] => 571748 [rel_patent_id] =>[rel_patent_doc_number] =>)