Search

Michelle F. Paguio Frising

Examiner (ID: 18931, Phone: (571)272-6224 , Office: P/1651 )

Most Active Art Unit
1651
Art Unit(s)
1651
Total Applications
651
Issued Applications
402
Pending Applications
73
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3125712 [patent_doc_number] => 05414812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'System for using object-oriented hierarchical representation to implement a configuration database for a layered computer network communications subsystem' [patent_app_type] => 1 [patent_app_number] => 8/296990 [patent_app_country] => US [patent_app_date] => 1994-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13286 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414812.pdf [firstpage_image] =>[orig_patent_app_number] => 296990 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/296990
System for using object-oriented hierarchical representation to implement a configuration database for a layered computer network communications subsystem Aug 25, 1994 Issued
Array ( [id] => 3855350 [patent_doc_number] => 05708850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock' [patent_app_type] => 1 [patent_app_number] => 8/280983 [patent_app_country] => US [patent_app_date] => 1994-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4016 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708850.pdf [firstpage_image] =>[orig_patent_app_number] => 280983 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280983
Parallel processing system for time division multiplex data transfer including read/write dual port memory accessible to bus and digital signal processor during opposite phases of clock Jul 26, 1994 Issued
Array ( [id] => 3741580 [patent_doc_number] => 05671377 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'System for supplying streams of data to multiple users by distributing a data stream to multiple processors and enabling each user to manipulate supplied data stream' [patent_app_type] => 1 [patent_app_number] => 8/275742 [patent_app_country] => US [patent_app_date] => 1994-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10774 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671377.pdf [firstpage_image] =>[orig_patent_app_number] => 275742 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/275742
System for supplying streams of data to multiple users by distributing a data stream to multiple processors and enabling each user to manipulate supplied data stream Jul 18, 1994 Issued
08/274746 METHOD FOR AUTOMATICALLY SETTING ADDRESS INFORMATION AND NETWORK ENVIRONMENT INFORMATION AND SYSTEM USING THE METHOD Jul 13, 1994 Abandoned
Array ( [id] => 3487528 [patent_doc_number] => 05428812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Data driven processors system for adaptively configuring width of the destination field based on the number of detected information processors' [patent_app_type] => 1 [patent_app_number] => 8/265621 [patent_app_country] => US [patent_app_date] => 1994-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4749 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428812.pdf [firstpage_image] =>[orig_patent_app_number] => 265621 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/265621
Data driven processors system for adaptively configuring width of the destination field based on the number of detected information processors Jun 23, 1994 Issued
Array ( [id] => 3746063 [patent_doc_number] => 05694619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'System for exclusively controlling access of a semiconductor memory module using a backup memory and compression and decompression techniques' [patent_app_type] => 1 [patent_app_number] => 8/261851 [patent_app_country] => US [patent_app_date] => 1994-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 53 [patent_no_of_words] => 18578 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694619.pdf [firstpage_image] =>[orig_patent_app_number] => 261851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/261851
System for exclusively controlling access of a semiconductor memory module using a backup memory and compression and decompression techniques Jun 15, 1994 Issued
Array ( [id] => 3523843 [patent_doc_number] => 05564021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Method for assigning inter-nodal traffic loads to channels in sonet rings' [patent_app_type] => 1 [patent_app_number] => 8/252035 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6825 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/564/05564021.pdf [firstpage_image] =>[orig_patent_app_number] => 252035 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252035
Method for assigning inter-nodal traffic loads to channels in sonet rings May 30, 1994 Issued
Array ( [id] => 3888532 [patent_doc_number] => 05838996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'System for determining presence of hardware decompression, selectively enabling hardware-based and software-based decompression, and conditioning the hardware when hardware decompression is available' [patent_app_type] => 1 [patent_app_number] => 8/251498 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5509 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838996.pdf [firstpage_image] =>[orig_patent_app_number] => 251498 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/251498
System for determining presence of hardware decompression, selectively enabling hardware-based and software-based decompression, and conditioning the hardware when hardware decompression is available May 30, 1994 Issued
Array ( [id] => 3755345 [patent_doc_number] => 05787246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'System for configuring devices for a computer system' [patent_app_type] => 1 [patent_app_number] => 8/250698 [patent_app_country] => US [patent_app_date] => 1994-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 25391 [patent_no_of_claims] => 98 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787246.pdf [firstpage_image] =>[orig_patent_app_number] => 250698 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/250698
System for configuring devices for a computer system May 26, 1994 Issued
Array ( [id] => 3521477 [patent_doc_number] => 05588117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Sender-selective send/receive order processing on a per message basis' [patent_app_type] => 1 [patent_app_number] => 8/247387 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3384 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/588/05588117.pdf [firstpage_image] =>[orig_patent_app_number] => 247387 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247387
Sender-selective send/receive order processing on a per message basis May 22, 1994 Issued
Array ( [id] => 3807585 [patent_doc_number] => 05842041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Computer system employing a control signal indicative of whether address is within address space of devices on processor local bus' [patent_app_type] => 1 [patent_app_number] => 8/246673 [patent_app_country] => US [patent_app_date] => 1994-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4417 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/842/05842041.pdf [firstpage_image] =>[orig_patent_app_number] => 246673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/246673
Computer system employing a control signal indicative of whether address is within address space of devices on processor local bus May 19, 1994 Issued
Array ( [id] => 3626136 [patent_doc_number] => 05566349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Complementary concurrent cooperative multi-processing multi-tasking processing system using shared memories with a minimum of four complementary processors' [patent_app_type] => 1 [patent_app_number] => 8/243174 [patent_app_country] => US [patent_app_date] => 1994-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 22759 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566349.pdf [firstpage_image] =>[orig_patent_app_number] => 243174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/243174
Complementary concurrent cooperative multi-processing multi-tasking processing system using shared memories with a minimum of four complementary processors May 15, 1994 Issued
08/234160 METHOD AND DEVICE FOR AUTOMATICALLY CHANGING THE OPERATING CONDITIONS OF MACHINES AND APPARATUS Apr 27, 1994 Abandoned
Array ( [id] => 3702452 [patent_doc_number] => 05664223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively' [patent_app_type] => 1 [patent_app_number] => 8/223144 [patent_app_country] => US [patent_app_date] => 1994-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664223.pdf [firstpage_image] =>[orig_patent_app_number] => 223144 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/223144
System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively Apr 4, 1994 Issued
Array ( [id] => 3734784 [patent_doc_number] => 05682529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'System for dynamically accommodating changes in display configuration by notifying changes to currently running application programs to generate information by application programs to conform to changed configuration' [patent_app_type] => 1 [patent_app_number] => 8/209275 [patent_app_country] => US [patent_app_date] => 1994-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5164 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682529.pdf [firstpage_image] =>[orig_patent_app_number] => 209275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/209275
System for dynamically accommodating changes in display configuration by notifying changes to currently running application programs to generate information by application programs to conform to changed configuration Mar 13, 1994 Issued
08/202391 ATA/IDE PROGRAMMABLE HARD DISC CONTROLLER SEQUENCER Feb 24, 1994 Abandoned
08/177582 SELF-DESCRIBING DATA PROCESSING SYSTEM Jan 4, 1994 Abandoned
Array ( [id] => 3635145 [patent_doc_number] => 05613067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Method and apparatus for assuring that multiple messages in a multi-node network are assured fair access to an outgoing data stream' [patent_app_type] => 1 [patent_app_number] => 8/176042 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4851 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/613/05613067.pdf [firstpage_image] =>[orig_patent_app_number] => 176042 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/176042
Method and apparatus for assuring that multiple messages in a multi-node network are assured fair access to an outgoing data stream Dec 29, 1993 Issued
Array ( [id] => 3642786 [patent_doc_number] => 05687389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'System for controlling an automatic read operation of read cache control circuit in a disk drive controller utilizing a start counter, a working counter, and a sector counter' [patent_app_type] => 1 [patent_app_number] => 8/173529 [patent_app_country] => US [patent_app_date] => 1993-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14632 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687389.pdf [firstpage_image] =>[orig_patent_app_number] => 173529 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/173529
System for controlling an automatic read operation of read cache control circuit in a disk drive controller utilizing a start counter, a working counter, and a sector counter Dec 21, 1993 Issued
08/172046 DATA MANAGEMENT METHOD AND ARCHITECTURE Dec 21, 1993 Abandoned
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