Search

Michelle F. Paguio Frising

Examiner (ID: 18931, Phone: (571)272-6224 , Office: P/1651 )

Most Active Art Unit
1651
Art Unit(s)
1651
Total Applications
651
Issued Applications
402
Pending Applications
73
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6417470 [patent_doc_number] => 20020125858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Apparatus for delivering the power status data of a smart battery' [patent_app_type] => new [patent_app_number] => 10/084155 [patent_app_country] => US [patent_app_date] => 2002-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2560 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20020125858.pdf [firstpage_image] =>[orig_patent_app_number] => 10084155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/084155
Apparatus for delivering the power status data of a smart battery Feb 27, 2002 Issued
Array ( [id] => 6452335 [patent_doc_number] => 20020129286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Microcomputer' [patent_app_type] => new [patent_app_number] => 10/085013 [patent_app_country] => US [patent_app_date] => 2002-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2773 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20020129286.pdf [firstpage_image] =>[orig_patent_app_number] => 10085013 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/085013
Microcomputer comprising electric power source without condenser for backup for changing power source level based on power supply stopped or resumed Feb 27, 2002 Issued
Array ( [id] => 1030628 [patent_doc_number] => 06883094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Communication device for monitoring datalink layer information and outputting data based on communication request information type' [patent_app_type] => utility [patent_app_number] => 10/083758 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8237 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883094.pdf [firstpage_image] =>[orig_patent_app_number] => 10083758 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083758
Communication device for monitoring datalink layer information and outputting data based on communication request information type Feb 25, 2002 Issued
Array ( [id] => 945859 [patent_doc_number] => 06968468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Digital computer utilizing buffer to store and output data to play real time applications enabling processor to enter deep sleep state while buffer outputs data' [patent_app_type] => utility [patent_app_number] => 10/082782 [patent_app_country] => US [patent_app_date] => 2002-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5206 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/968/06968468.pdf [firstpage_image] =>[orig_patent_app_number] => 10082782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082782
Digital computer utilizing buffer to store and output data to play real time applications enabling processor to enter deep sleep state while buffer outputs data Feb 24, 2002 Issued
Array ( [id] => 937590 [patent_doc_number] => 06976160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Method and system for controlling default values of flip-flops in PGA/ASIC-based designs' [patent_app_type] => utility [patent_app_number] => 10/082630 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3418 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976160.pdf [firstpage_image] =>[orig_patent_app_number] => 10082630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082630
Method and system for controlling default values of flip-flops in PGA/ASIC-based designs Feb 21, 2002 Issued
Array ( [id] => 1001772 [patent_doc_number] => 06912664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Energy-aware software-controlled plurality of displays' [patent_app_type] => utility [patent_app_number] => 10/081720 [patent_app_country] => US [patent_app_date] => 2002-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10907 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912664.pdf [firstpage_image] =>[orig_patent_app_number] => 10081720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/081720
Energy-aware software-controlled plurality of displays Feb 20, 2002 Issued
Array ( [id] => 1183417 [patent_doc_number] => 06751687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Method of controlling device, transmission device, and medium' [patent_app_type] => B1 [patent_app_number] => 09/857279 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 38 [patent_no_of_words] => 14013 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751687.pdf [firstpage_image] =>[orig_patent_app_number] => 09857279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/857279
Method of controlling device, transmission device, and medium Feb 7, 2002 Issued
Array ( [id] => 7611311 [patent_doc_number] => 06904531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Portable computer with low power consumption of a card bus controller thereof' [patent_app_type] => utility [patent_app_number] => 09/683693 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1109 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904531.pdf [firstpage_image] =>[orig_patent_app_number] => 09683693 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683693
Portable computer with low power consumption of a card bus controller thereof Feb 4, 2002 Issued
Array ( [id] => 6789023 [patent_doc_number] => 20030140262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Switching power planes of external device interfaces in a computing system in response to connection status' [patent_app_type] => new [patent_app_number] => 10/055054 [patent_app_country] => US [patent_app_date] => 2002-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20030140262.pdf [firstpage_image] =>[orig_patent_app_number] => 10055054 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/055054
Switching power planes of external device interfaces in a computing system in response to connection status Jan 22, 2002 Issued
Array ( [id] => 6789020 [patent_doc_number] => 20030140259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Method for recording power failure time of a computer system' [patent_app_type] => new [patent_app_number] => 09/683576 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20030140259.pdf [firstpage_image] =>[orig_patent_app_number] => 09683576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683576
Method for recording power failure time of a computer system Jan 21, 2002 Issued
Array ( [id] => 6389020 [patent_doc_number] => 20020120836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Method for switching between boot devices in information processing unit' [patent_app_type] => new [patent_app_number] => 10/054529 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5445 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20020120836.pdf [firstpage_image] =>[orig_patent_app_number] => 10054529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/054529
Method for switching between boot devices in information processing unit Jan 21, 2002 Issued
Array ( [id] => 7175202 [patent_doc_number] => 20040078706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Bus interface timing adjustment device, method and application chip' [patent_app_type] => new [patent_app_number] => 10/055567 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9852 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078706.pdf [firstpage_image] =>[orig_patent_app_number] => 10055567 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/055567
Bus interface timing adjustment device, method and application chip Jan 21, 2002 Issued
Array ( [id] => 975529 [patent_doc_number] => 06938172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Data transformation for the reduction of power and noise in CMOS structures' [patent_app_type] => utility [patent_app_number] => 10/054557 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2290 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/938/06938172.pdf [firstpage_image] =>[orig_patent_app_number] => 10054557 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/054557
Data transformation for the reduction of power and noise in CMOS structures Jan 17, 2002 Issued
Array ( [id] => 6631873 [patent_doc_number] => 20020065971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Memory unit and method of assembling a computer' [patent_app_type] => new [patent_app_number] => 10/039085 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3208 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20020065971.pdf [firstpage_image] =>[orig_patent_app_number] => 10039085 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/039085
Memory unit and method of assembling a computer Jan 3, 2002 Issued
Array ( [id] => 981734 [patent_doc_number] => 06931559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Multiple mode power throttle mechanism' [patent_app_type] => utility [patent_app_number] => 10/041013 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4783 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/931/06931559.pdf [firstpage_image] =>[orig_patent_app_number] => 10041013 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/041013
Multiple mode power throttle mechanism Dec 27, 2001 Issued
Array ( [id] => 5848290 [patent_doc_number] => 20020133647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Watermark for additional data burst into buffer memory' [patent_app_type] => new [patent_app_number] => 10/005509 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 14591 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133647.pdf [firstpage_image] =>[orig_patent_app_number] => 10005509 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005509
Watermark for additional data burst into buffer memory Dec 3, 2001 Issued
Array ( [id] => 981732 [patent_doc_number] => 06931558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-16 [patent_title] => 'Computer restoration systems and methods' [patent_app_type] => utility [patent_app_number] => 09/998246 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5262 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/931/06931558.pdf [firstpage_image] =>[orig_patent_app_number] => 09998246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998246
Computer restoration systems and methods Nov 29, 2001 Issued
Array ( [id] => 1040062 [patent_doc_number] => 06874098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 09/995657 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 11158 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/874/06874098.pdf [firstpage_image] =>[orig_patent_app_number] => 09995657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/995657
Semiconductor integrated circuit Nov 28, 2001 Issued
Array ( [id] => 6559009 [patent_doc_number] => 20020111696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Method and device for synchronizing processes which are performed on a plurality of units' [patent_app_type] => new [patent_app_number] => 09/997981 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4704 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20020111696.pdf [firstpage_image] =>[orig_patent_app_number] => 09997981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997981
Method and device for synchronizing processes which are performed on a plurality of units Nov 28, 2001 Issued
Array ( [id] => 6766963 [patent_doc_number] => 20030101363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Method and system for minimizing power consumption in embedded systems with clock enable control' [patent_app_type] => new [patent_app_number] => 09/996094 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4258 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101363.pdf [firstpage_image] =>[orig_patent_app_number] => 09996094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996094
Method and system for minimizing power consumption in embedded systems with clock enable control Nov 26, 2001 Abandoned
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