Search

Michelle F. Paguio Frising

Examiner (ID: 18931, Phone: (571)272-6224 , Office: P/1651 )

Most Active Art Unit
1651
Art Unit(s)
1651
Total Applications
651
Issued Applications
402
Pending Applications
73
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1062277 [patent_doc_number] => 06854067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-08 [patent_title] => 'Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller' [patent_app_type] => utility [patent_app_number] => 09/887923 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/854/06854067.pdf [firstpage_image] =>[orig_patent_app_number] => 09887923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/887923
Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller Jun 21, 2001 Issued
Array ( [id] => 6737047 [patent_doc_number] => 20030014682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Clock generation systems and methods' [patent_app_type] => new [patent_app_number] => 09/887905 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014682.pdf [firstpage_image] =>[orig_patent_app_number] => 09887905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/887905
Clock generation systems and methods Jun 21, 2001 Issued
Array ( [id] => 1106153 [patent_doc_number] => 06816929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Data transfer control method and controller for universal serial bus interface' [patent_app_type] => B2 [patent_app_number] => 09/884128 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 11393 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816929.pdf [firstpage_image] =>[orig_patent_app_number] => 09884128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884128
Data transfer control method and controller for universal serial bus interface Jun 19, 2001 Issued
Array ( [id] => 6899274 [patent_doc_number] => 20010047439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Efficient implementation of first-in-first-out memories for multi-processor systems' [patent_app_type] => new [patent_app_number] => 09/881512 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5474 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047439.pdf [firstpage_image] =>[orig_patent_app_number] => 09881512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/881512
Efficient implementation of first-in-first-out memories for multi-processor systems Jun 13, 2001 Issued
Array ( [id] => 5803594 [patent_doc_number] => 20020010881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Method and system for enhancing fibre channel loop resiliency for a mass storage enclosure by increasing component redundancy and using shunt elements and intelligent bypass management' [patent_app_type] => new [patent_app_number] => 09/872510 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010881.pdf [firstpage_image] =>[orig_patent_app_number] => 09872510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/872510
Method and system for enhancing fibre channel loop resiliency for a mass storage enclosure by increasing component redundancy and using shunt elements and intelligent bypass management May 31, 2001 Abandoned
Array ( [id] => 1119918 [patent_doc_number] => 06801959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Relaxed-timing universal serial bus with a start of frame packet generator' [patent_app_type] => B1 [patent_app_number] => 09/858957 [patent_app_country] => US [patent_app_date] => 2001-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3762 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801959.pdf [firstpage_image] =>[orig_patent_app_number] => 09858957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/858957
Relaxed-timing universal serial bus with a start of frame packet generator May 15, 2001 Issued
Array ( [id] => 6108760 [patent_doc_number] => 20020171856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Method for automatically detecting and processing binary postscript print jobs' [patent_app_type] => new [patent_app_number] => 09/855283 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6865 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20020171856.pdf [firstpage_image] =>[orig_patent_app_number] => 09855283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/855283
Method for automatically detecting and processing binary postscript print jobs May 14, 2001 Issued
Array ( [id] => 1068353 [patent_doc_number] => 06848046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'SMM loader and execution mechanism for component software for multiple architectures' [patent_app_type] => utility [patent_app_number] => 09/854174 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6298 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/848/06848046.pdf [firstpage_image] =>[orig_patent_app_number] => 09854174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854174
SMM loader and execution mechanism for component software for multiple architectures May 10, 2001 Issued
Array ( [id] => 7610003 [patent_doc_number] => 06842856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'System and method for dynamic management of a startup sequence' [patent_app_type] => utility [patent_app_number] => 09/854279 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5497 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842856.pdf [firstpage_image] =>[orig_patent_app_number] => 09854279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854279
System and method for dynamic management of a startup sequence May 10, 2001 Issued
Array ( [id] => 6226868 [patent_doc_number] => 20020004916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Methods and apparatus for power control in a scalable array of processor elements' [patent_app_type] => new [patent_app_number] => 09/853989 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8550 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004916.pdf [firstpage_image] =>[orig_patent_app_number] => 09853989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853989
Methods and apparatus for power control in a scalable array of processor elements May 10, 2001 Issued
Array ( [id] => 6460666 [patent_doc_number] => 20020178351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Mechanism for eliminating need for flash memory in software RAID' [patent_app_type] => new [patent_app_number] => 09/853310 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1531 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178351.pdf [firstpage_image] =>[orig_patent_app_number] => 09853310 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853310
Mechanism for eliminating need for flash memory in software RAID May 10, 2001 Issued
Array ( [id] => 6899327 [patent_doc_number] => 20010047492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Uninterruptible power supply for automatically storing computer data in hard disk when halting' [patent_app_type] => new [patent_app_number] => 09/852045 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1696 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047492.pdf [firstpage_image] =>[orig_patent_app_number] => 09852045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/852045
Uninterruptible power supply for automatically storing computer data in hard disk when halting May 9, 2001 Abandoned
Array ( [id] => 1180760 [patent_doc_number] => 06754741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Flexible FIFO system for interfacing between datapaths of variable length' [patent_app_type] => B2 [patent_app_number] => 09/854075 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 13118 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754741.pdf [firstpage_image] =>[orig_patent_app_number] => 09854075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854075
Flexible FIFO system for interfacing between datapaths of variable length May 9, 2001 Issued
Array ( [id] => 6099258 [patent_doc_number] => 20020053073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Upgrading device and method of upgrading' [patent_app_type] => new [patent_app_number] => 09/849996 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6478 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053073.pdf [firstpage_image] =>[orig_patent_app_number] => 09849996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849996
Upgrading device and method of upgrading May 7, 2001 Issued
Array ( [id] => 6885461 [patent_doc_number] => 20010039626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Configuration for identifying a switch position of a power switch' [patent_app_type] => new [patent_app_number] => 09/851054 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3397 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039626.pdf [firstpage_image] =>[orig_patent_app_number] => 09851054 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851054
Configuration for identifying a switch position of a power switch May 7, 2001 Issued
Array ( [id] => 1112119 [patent_doc_number] => 06810448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Method and apparatus for processing chain messages (SGL chaining)' [patent_app_type] => B1 [patent_app_number] => 09/848569 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3745 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810448.pdf [firstpage_image] =>[orig_patent_app_number] => 09848569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/848569
Method and apparatus for processing chain messages (SGL chaining) May 1, 2001 Issued
Array ( [id] => 1062250 [patent_doc_number] => 06854053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Method for identifying and communicating with a plurality of slaves in a master-slave system' [patent_app_type] => utility [patent_app_number] => 09/848011 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4201 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/854/06854053.pdf [firstpage_image] =>[orig_patent_app_number] => 09848011 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/848011
Method for identifying and communicating with a plurality of slaves in a master-slave system May 1, 2001 Issued
Array ( [id] => 7016120 [patent_doc_number] => 20010052041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Automation system and method for accessing the functionality of hardware components' [patent_app_type] => new [patent_app_number] => 09/846395 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3514 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052041.pdf [firstpage_image] =>[orig_patent_app_number] => 09846395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/846395
Automation system to access functionality of hardware components with each hardware component having system connection unit with function objects representing real functionality of components May 1, 2001 Issued
Array ( [id] => 5791415 [patent_doc_number] => 20020161941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'System and method for efficiently performing a data transfer operation' [patent_app_type] => new [patent_app_number] => 09/846906 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4826 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20020161941.pdf [firstpage_image] =>[orig_patent_app_number] => 09846906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/846906
System and method for efficiently performing a data transfer operation Apr 29, 2001 Abandoned
Array ( [id] => 7622393 [patent_doc_number] => 06687773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Bridge for coupling digital signal processor to on-chip bus as master' [patent_app_type] => B1 [patent_app_number] => 09/847849 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 8111 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687773.pdf [firstpage_image] =>[orig_patent_app_number] => 09847849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847849
Bridge for coupling digital signal processor to on-chip bus as master Apr 29, 2001 Issued
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