Search

Michelle J. Lee

Examiner (ID: 2718, Phone: (571)270-7303 , Office: P/3772 )

Most Active Art Unit
3786
Art Unit(s)
3786, 3772, 3793
Total Applications
493
Issued Applications
202
Pending Applications
60
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11621962 [patent_doc_number] => 20170132150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'Memory Controller For Selective Rank Or Subrank Access' [patent_app_type] => utility [patent_app_number] => 15/295723 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9789 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15295723 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/295723
Memory Controller For Selective Rank Or Subrank Access Oct 16, 2016 Abandoned
Array ( [id] => 12228999 [patent_doc_number] => 09916244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-13 [patent_title] => 'Techniques for maintaining cache coherence by atomically processing groups of storage commands' [patent_app_type] => utility [patent_app_number] => 15/282209 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7695 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282209 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/282209
Techniques for maintaining cache coherence by atomically processing groups of storage commands Sep 29, 2016 Issued
Array ( [id] => 12249196 [patent_doc_number] => 09921972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Method and apparatus for implementing a heterogeneous memory subsystem' [patent_app_type] => utility [patent_app_number] => 15/281383 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 10111 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281383
Method and apparatus for implementing a heterogeneous memory subsystem Sep 29, 2016 Issued
Array ( [id] => 13974141 [patent_doc_number] => 10216425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Topology aware load optimized multipath I/O scheduler [patent_app_type] => utility [patent_app_number] => 15/282568 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282568 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/282568
Topology aware load optimized multipath I/O scheduler Sep 29, 2016 Issued
Array ( [id] => 11384911 [patent_doc_number] => 20170010967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'USING L1 CACHE AS RE-ORDER BUFFER' [patent_app_type] => utility [patent_app_number] => 15/270018 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7160 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270018 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270018
Using L1 cache as re-order buffer Sep 19, 2016 Issued
Array ( [id] => 13171659 [patent_doc_number] => 10101944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Solid state storage device and data writing method thereof [patent_app_type] => utility [patent_app_number] => 15/262599 [patent_app_country] => US [patent_app_date] => 2016-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7775 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15262599 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/262599
Solid state storage device and data writing method thereof Sep 11, 2016 Issued
Array ( [id] => 11329805 [patent_doc_number] => 20160360417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'STORAGE DEVICE WITH ACCESS CONTROL DEVICE AND METHOD FOR ACCESSING STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/242613 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5162 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15242613 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/242613
STORAGE DEVICE WITH ACCESS CONTROL DEVICE AND METHOD FOR ACCESSING STORAGE DEVICE Aug 21, 2016 Abandoned
Array ( [id] => 15317683 [patent_doc_number] => 10523566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 15/753826 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 10041 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15753826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/753826
Memory device Aug 8, 2016 Issued
Array ( [id] => 11423684 [patent_doc_number] => 20170031828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'SYSTEMS AND METHODS FOR COORDINATING INTERDEPENDENT ASYNCHRONOUS READS' [patent_app_type] => utility [patent_app_number] => 15/222640 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222640 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222640
Systems and methods for coordinating interdependent asynchronous reads Jul 27, 2016 Issued
Array ( [id] => 12331491 [patent_doc_number] => 09946490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Bit-level indirection defragmentation [patent_app_type] => utility [patent_app_number] => 15/222504 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222504 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222504
Bit-level indirection defragmentation Jul 27, 2016 Issued
Array ( [id] => 15077185 [patent_doc_number] => 10468087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Apparatuses and methods for operations in a self-refresh state [patent_app_type] => utility [patent_app_number] => 15/222514 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 16769 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222514 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222514
Apparatuses and methods for operations in a self-refresh state Jul 27, 2016 Issued
Array ( [id] => 12140199 [patent_doc_number] => 20180018282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'INCREASING THE SCOPE OF LOCAL PURGES OF STRUCTURES ASSOCIATED WITH ADDRESS TRANSLATION' [patent_app_type] => utility [patent_app_number] => 15/212546 [patent_app_country] => US [patent_app_date] => 2016-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/212546
Increasing the scope of local purges of structures associated with address translation Jul 17, 2016 Issued
Array ( [id] => 12140192 [patent_doc_number] => 20180018275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'REDUCING OVER-PURGING OF STRUCTURES ASSOCIATED WITH ADDRESS TRANSLATION' [patent_app_type] => utility [patent_app_number] => 15/212347 [patent_app_country] => US [patent_app_date] => 2016-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212347 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/212347
Reducing over-purging of structures associated with address translation Jul 17, 2016 Issued
Array ( [id] => 16032081 [patent_doc_number] => 10678459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => High performance, high capacity memory modules and systems [patent_app_type] => utility [patent_app_number] => 15/745396 [patent_app_country] => US [patent_app_date] => 2016-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 8520 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15745396 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/745396
High performance, high capacity memory modules and systems Jul 13, 2016 Issued
Array ( [id] => 12433680 [patent_doc_number] => 09977741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Fusible and reconfigurable cache architecture [patent_app_type] => utility [patent_app_number] => 15/208295 [patent_app_country] => US [patent_app_date] => 2016-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6079 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208295 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/208295
Fusible and reconfigurable cache architecture Jul 11, 2016 Issued
Array ( [id] => 11423465 [patent_doc_number] => 20170031609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'INFORMATION PROCESSING DEVICE, RECORDING MEDIUM AND ACCESS INFORMATION MANAGEMENT METHOD' [patent_app_type] => utility [patent_app_number] => 15/168686 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6453 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15168686 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/168686
INFORMATION PROCESSING DEVICE, RECORDING MEDIUM AND ACCESS INFORMATION MANAGEMENT METHOD May 30, 2016 Abandoned
Array ( [id] => 13199665 [patent_doc_number] => 10114751 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-30 [patent_title] => Method and system for implementing cache size estimations [patent_app_type] => utility [patent_app_number] => 15/169381 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10999 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169381 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169381
Method and system for implementing cache size estimations May 30, 2016 Issued
Array ( [id] => 11868386 [patent_doc_number] => 20170235671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'COMPUTING DEVICE, DATA TRANSFER METHOD BETWEEN COPROCESSOR AND NON-VOLATILE MEMORY, AND COMPUTER-READABLE RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/168423 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15168423 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/168423
Computing device, data transfer method between coprocessor and non-volatile memory, and computer-readable recording medium May 30, 2016 Issued
Array ( [id] => 11951267 [patent_doc_number] => 20170255418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'MEMORY SYSTEM AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/169609 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169609 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169609
Memory system and method of controlling the same May 30, 2016 Issued
Array ( [id] => 11013105 [patent_doc_number] => 20160210058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'USING EXTERNAL MEMORY DEVICES TO IMPROVE SYSTEM PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 15/080357 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15080357 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/080357
Using external memory devices to improve system performance Mar 23, 2016 Issued
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