Search

Michelle J. Lee

Examiner (ID: 18654, Phone: (571)270-7303 , Office: P/3772 )

Most Active Art Unit
3786
Art Unit(s)
3786, 3772, 3793
Total Applications
507
Issued Applications
210
Pending Applications
59
Abandoned Applications
253

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19434906 [patent_doc_number] => 20240303404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => USING MACHINE VISION TO SOLVE INDUSTRIAL BOOLEAN SATISFIABILITY (SAT) PROBLEMS [patent_app_type] => utility [patent_app_number] => 18/181200 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181200 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/181200
USING MACHINE VISION TO SOLVE INDUSTRIAL BOOLEAN SATISFIABILITY (SAT) PROBLEMS Mar 8, 2023 Pending
Array ( [id] => 18471680 [patent_doc_number] => 20230205966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => INTEGRATED CIRCUIT WITH THICKER METAL LINES ON LOWER METALLIZATION LAYER [patent_app_type] => utility [patent_app_number] => 18/173731 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/173731
Integrated circuit with thicker metal lines on lower metallization layer Feb 22, 2023 Issued
Array ( [id] => 19391711 [patent_doc_number] => 20240281581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => LIBRARY SCALING FOR CIRCUIT DESIGN ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/111263 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18111263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/111263
Library scaling for circuit design analysis Feb 16, 2023 Issued
Array ( [id] => 19006290 [patent_doc_number] => 20240070361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CIRCUIT ANALYSIS METHOD, CIRCUIT ANALYSIS DEVICE, AND CIRCUIT ANALYSIS SYSTEM [patent_app_type] => utility [patent_app_number] => 18/166055 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166055 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166055
Circuit analysis method, circuit analysis device, and circuit analysis system Feb 7, 2023 Issued
Array ( [id] => 20482039 [patent_doc_number] => 12530514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Method of designing ternary logic circuit using MOSFETs having depletion-mode and multi-VTHS, and device and recording medium for performing the same [patent_app_type] => utility [patent_app_number] => 18/096344 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 1464 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096344
Method of designing ternary logic circuit using MOSFETs having depletion-mode and multi-VTHS, and device and recording medium for performing the same Jan 11, 2023 Issued
Array ( [id] => 19303905 [patent_doc_number] => 20240232485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => TEST POINT INSERTION IN ANALOG CIRCUIT DESIGN TESTING [patent_app_type] => utility [patent_app_number] => 18/094951 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/094951
Test point insertion in analog circuit design testing Jan 8, 2023 Issued
Array ( [id] => 19303906 [patent_doc_number] => 20240232486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => USING SURROGATE NETLISTS FOR VARIATION ANALYSIS OF PROCESS VARIATIONS [patent_app_type] => utility [patent_app_number] => 18/152069 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152069
Using surrogate netlists for variation analysis of process variations Jan 8, 2023 Issued
Array ( [id] => 18864571 [patent_doc_number] => 20230419008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => METHOD FOR DETERMINING PERFORMANCE OF SEQUENTIAL LOGIC ELEMENTS AND DEVICE [patent_app_type] => utility [patent_app_number] => 18/094100 [patent_app_country] => US [patent_app_date] => 2023-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/094100
METHOD FOR DETERMINING PERFORMANCE OF SEQUENTIAL LOGIC ELEMENTS AND DEVICE Jan 5, 2023 Pending
Array ( [id] => 19284221 [patent_doc_number] => 20240220697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => AUTOMATED DESIGN-TO-LITHOGRAPHY AND DESIGN CHECKING FOR STITCHED INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 18/092130 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092130
AUTOMATED DESIGN-TO-LITHOGRAPHY AND DESIGN CHECKING FOR STITCHED INTEGRATED CIRCUIT DESIGN Dec 29, 2022 Pending
Array ( [id] => 19284223 [patent_doc_number] => 20240220699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => METHODS AND APPARATUS TO AUTOMATE A DESIGN INCLUDING ROUTING BETWEEN DICE [patent_app_type] => utility [patent_app_number] => 18/148963 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148963 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148963
METHODS AND APPARATUS TO AUTOMATE A DESIGN INCLUDING ROUTING BETWEEN DICE Dec 29, 2022 Pending
Array ( [id] => 19284214 [patent_doc_number] => 20240220690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => Synthesis and Verification of an Integrated Circuit (IC) [patent_app_type] => utility [patent_app_number] => 18/091755 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091755 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091755
Synthesis and Verification of an Integrated Circuit (IC) Dec 29, 2022 Pending
Array ( [id] => 18298653 [patent_doc_number] => 20230108339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => Circuit Implementation on Processing Circuitry [patent_app_type] => utility [patent_app_number] => 18/077187 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077187
Circuit Implementation on Processing Circuitry Dec 6, 2022 Issued
Array ( [id] => 18668814 [patent_doc_number] => 11775718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Methods and apparatus to simulate metastability for circuit design verification [patent_app_type] => utility [patent_app_number] => 18/072842 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 13993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072842 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/072842
Methods and apparatus to simulate metastability for circuit design verification Nov 30, 2022 Issued
Array ( [id] => 18881706 [patent_doc_number] => 20240005075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => GRAPHIC NEURAL NETWORK ACCELERATION SOLUTION WITH CUSTOMIZED BOARD FOR SOLID-STATE DRIVES [patent_app_type] => utility [patent_app_number] => 18/071970 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/071970
GRAPHIC NEURAL NETWORK ACCELERATION SOLUTION WITH CUSTOMIZED BOARD FOR SOLID-STATE DRIVES Nov 29, 2022 Pending
Array ( [id] => 18711580 [patent_doc_number] => 20230334209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => CIRCUIT VERIFICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/059961 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/059961
Circuit verification method Nov 28, 2022 Issued
Array ( [id] => 20388438 [patent_doc_number] => 12488166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Implementing burst transfers for predicated memory accesses in loop bodies for high-level synthesis [patent_app_type] => utility [patent_app_number] => 18/059348 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/059348
Implementing burst transfers for predicated memory accesses in loop bodies for high-level synthesis Nov 27, 2022 Issued
Array ( [id] => 19291053 [patent_doc_number] => 12030397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Cord reel variable current thermal management and damage detection [patent_app_type] => utility [patent_app_number] => 17/991967 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2920 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17991967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/991967
Cord reel variable current thermal management and damage detection Nov 21, 2022 Issued
Array ( [id] => 18788228 [patent_doc_number] => 20230376659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => VLSI PLACEMENT OPTIMIZATION USING SELF-SUPERVISED GRAPH CLUSTERING [patent_app_type] => utility [patent_app_number] => 18/051984 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051984
VLSI placement optimization using self-supervised graph clustering Nov 1, 2022 Issued
Array ( [id] => 18471678 [patent_doc_number] => 20230205964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => LAYOUT METHOD AND RELATED NON-TRANSITORY COMPUTER-READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/049486 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/049486
Layout method and related non-transitory computer-readable medium Oct 24, 2022 Issued
Array ( [id] => 18644377 [patent_doc_number] => 11768442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Method of determining control parameters of a device manufacturing process [patent_app_type] => utility [patent_app_number] => 17/973221 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 40 [patent_no_of_words] => 26965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973221 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/973221
Method of determining control parameters of a device manufacturing process Oct 24, 2022 Issued
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