Search

Michelle J. Lee

Examiner (ID: 18654, Phone: (571)270-7303 , Office: P/3772 )

Most Active Art Unit
3786
Art Unit(s)
3786, 3772, 3793
Total Applications
507
Issued Applications
210
Pending Applications
59
Abandoned Applications
253

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19303910 [patent_doc_number] => 20240232490 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SYSTEM AND METHOD OF CONFIGURING INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/047926 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047926
System and method of configuring integrated circuits Oct 18, 2022 Issued
Array ( [id] => 19303910 [patent_doc_number] => 20240232490 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SYSTEM AND METHOD OF CONFIGURING INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/047926 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047926
System and method of configuring integrated circuits Oct 18, 2022 Issued
Array ( [id] => 18223244 [patent_doc_number] => 20230062238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Pooling Processing Method and System Applied to Convolutional Neural Network [patent_app_type] => utility [patent_app_number] => 18/047716 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047716
Pooling processing method and system applied to convolutional neural network Oct 18, 2022 Issued
Array ( [id] => 18307297 [patent_doc_number] => 20230111197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => PIN SHARING FOR PHOTONIC PROCESSORS [patent_app_type] => utility [patent_app_number] => 17/967314 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17967314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/967314
PIN SHARING FOR PHOTONIC PROCESSORS Oct 16, 2022 Pending
Array ( [id] => 18999549 [patent_doc_number] => 11916411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Modular charging system and wall-mounted charging device and modular power devices [patent_app_type] => utility [patent_app_number] => 17/963074 [patent_app_country] => US [patent_app_date] => 2022-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 42 [patent_no_of_words] => 10093 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17963074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/963074
Modular charging system and wall-mounted charging device and modular power devices Oct 9, 2022 Issued
Array ( [id] => 20243173 [patent_doc_number] => 12423493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Synthetic loading of configurable logic devices [patent_app_type] => utility [patent_app_number] => 17/962272 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/962272
Synthetic loading of configurable logic devices Oct 6, 2022 Issued
Array ( [id] => 18169379 [patent_doc_number] => 20230035990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => Modular Charging System and Wall-Mounted Charging Device and Modular Power Devices [patent_app_type] => utility [patent_app_number] => 17/961225 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961225 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961225
Modular charging system and wall-mounted charging device and modular power devices Oct 5, 2022 Issued
Array ( [id] => 19370831 [patent_doc_number] => 12062929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Modular charging system and wall-mounted charging device and modular power devices [patent_app_type] => utility [patent_app_number] => 17/960300 [patent_app_country] => US [patent_app_date] => 2022-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 42 [patent_no_of_words] => 10095 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17960300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/960300
Modular charging system and wall-mounted charging device and modular power devices Oct 4, 2022 Issued
Array ( [id] => 20331805 [patent_doc_number] => 12462082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Satisfying circuit design constraints using a combination of machine learning models [patent_app_type] => utility [patent_app_number] => 17/959038 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959038
Satisfying circuit design constraints using a combination of machine learning models Oct 2, 2022 Issued
Array ( [id] => 20583163 [patent_doc_number] => 12575426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Wafer-scale chip structure and method and system for designing the structure [patent_app_type] => utility [patent_app_number] => 17/935588 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 5025 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17935588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/935588
Wafer-scale chip structure and method and system for designing the structure Sep 26, 2022 Issued
Array ( [id] => 18281558 [patent_doc_number] => 20230097030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SYSTEMS AND METHODS OF AUTOMATIC GENERATION OF INTEGRATED CIRCUIT IP BLOCKS [patent_app_type] => utility [patent_app_number] => 17/953378 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953378
Systems and methods of automatic generation of integrated circuit IP blocks Sep 26, 2022 Issued
Array ( [id] => 20203340 [patent_doc_number] => 12406120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Multicycle path prediction of reset signals [patent_app_type] => utility [patent_app_number] => 17/954159 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954159 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954159
Multicycle path prediction of reset signals Sep 26, 2022 Issued
Array ( [id] => 19243635 [patent_doc_number] => 12014078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Apparatus and architecture of non-volatile memory module in parallel configuration [patent_app_type] => utility [patent_app_number] => 17/949845 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8322 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949845
Apparatus and architecture of non-volatile memory module in parallel configuration Sep 20, 2022 Issued
Array ( [id] => 18141967 [patent_doc_number] => 20230015810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => LAYOUT AND WIRING METHOD, COMPARISON METHOD, FABRICATION METHOD, DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/945233 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945233
LAYOUT AND WIRING METHOD, COMPARISON METHOD, FABRICATION METHOD, DEVICE, AND STORAGE MEDIUM Sep 14, 2022 Pending
Array ( [id] => 19053466 [patent_doc_number] => 20240095435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => ALGORITHMIC CIRCUIT DESIGN AUTOMATION [patent_app_type] => utility [patent_app_number] => 17/932538 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932538
Algorithmic circuit design automation Sep 14, 2022 Issued
Array ( [id] => 18695157 [patent_doc_number] => 20230325577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => METHOD VERIFYING PROCESS PROXIMITY CORRECTION USING MACHINE LEARNING, AND SEMICONDUCTOR MANUFACTURING METHOD USING SAME [patent_app_type] => utility [patent_app_number] => 17/903070 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/903070
Method verifying process proximity correction using machine learning, and semiconductor manufacturing method using same Sep 5, 2022 Issued
Array ( [id] => 18096100 [patent_doc_number] => 20220414441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => GENERAL PADDING SUPPORT FOR CONVOLUTION ON SYSTOLIC ARRAYS [patent_app_type] => utility [patent_app_number] => 17/902776 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902776
General padding support for convolution on systolic arrays Sep 1, 2022 Issued
Array ( [id] => 19872905 [patent_doc_number] => 12265767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => System and method for electronic circuit resimulation [patent_app_type] => utility [patent_app_number] => 17/893136 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5641 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893136
System and method for electronic circuit resimulation Aug 21, 2022 Issued
Array ( [id] => 20079744 [patent_doc_number] => 12353813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Accounting for steady state noise in bit response superposition based eye diagram simulation [patent_app_type] => utility [patent_app_number] => 17/883357 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883357
Accounting for steady state noise in bit response superposition based eye diagram simulation Aug 7, 2022 Issued
Array ( [id] => 18957688 [patent_doc_number] => 20240046015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => LATENCY BALANCING OF PATHS IN MULTI-PROCESSOR COMPUTING ARCHITECTURE DESIGNS FOR DEADLOCK AVOIDANCE [patent_app_type] => utility [patent_app_number] => 17/818341 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818341 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818341
Latency balancing of paths in multi-processor computing architecture designs for deadlock avoidance Aug 7, 2022 Issued
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