Search

Michelle J. Lee

Examiner (ID: 2718, Phone: (571)270-7303 , Office: P/3772 )

Most Active Art Unit
3786
Art Unit(s)
3786, 3772, 3793
Total Applications
493
Issued Applications
202
Pending Applications
60
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 451043 [patent_doc_number] => 07254666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'System and method for delivering information at inaccessible locations' [patent_app_type] => utility [patent_app_number] => 09/777729 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4657 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254666.pdf [firstpage_image] =>[orig_patent_app_number] => 09777729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777729
System and method for delivering information at inaccessible locations Feb 5, 2001 Issued
Array ( [id] => 725982 [patent_doc_number] => 07051173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Backup system and method thereof in disk shared file system' [patent_app_type] => utility [patent_app_number] => 09/752467 [patent_app_country] => US [patent_app_date] => 2001-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 12099 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051173.pdf [firstpage_image] =>[orig_patent_app_number] => 09752467 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752467
Backup system and method thereof in disk shared file system Jan 2, 2001 Issued
Array ( [id] => 6483392 [patent_doc_number] => 20020023139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Cache server network' [patent_app_type] => new [patent_app_number] => 09/748119 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2261 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20020023139.pdf [firstpage_image] =>[orig_patent_app_number] => 09748119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748119
Cache server network Dec 26, 2000 Abandoned
Array ( [id] => 6988456 [patent_doc_number] => 20010037357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Storage apparatus and access control method' [patent_app_type] => new [patent_app_number] => 09/736809 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12151 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037357.pdf [firstpage_image] =>[orig_patent_app_number] => 09736809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736809
Storage apparatus and access control method Dec 13, 2000 Issued
Array ( [id] => 1092804 [patent_doc_number] => 06829672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Electronic flash memory external storage method and device' [patent_app_type] => B1 [patent_app_number] => 09/687869 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6400 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829672.pdf [firstpage_image] =>[orig_patent_app_number] => 09687869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/687869
Electronic flash memory external storage method and device Oct 12, 2000 Issued
Array ( [id] => 739551 [patent_doc_number] => 07039766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-02 [patent_title] => 'Prescheduling sequential data prefetches in a preexisting LRU cache' [patent_app_type] => utility [patent_app_number] => 09/689488 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6205 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/039/07039766.pdf [firstpage_image] =>[orig_patent_app_number] => 09689488 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689488
Prescheduling sequential data prefetches in a preexisting LRU cache Oct 11, 2000 Issued
Array ( [id] => 7608128 [patent_doc_number] => 07000072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-14 [patent_title] => 'Cache memory allocation method' [patent_app_type] => utility [patent_app_number] => 09/688360 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 9686 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000072.pdf [firstpage_image] =>[orig_patent_app_number] => 09688360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/688360
Cache memory allocation method Oct 11, 2000 Issued
Array ( [id] => 1429215 [patent_doc_number] => 06529993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Data and data strobe circuits and operating protocol for double data rate memories' [patent_app_type] => B1 [patent_app_number] => 09/689090 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10119 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529993.pdf [firstpage_image] =>[orig_patent_app_number] => 09689090 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689090
Data and data strobe circuits and operating protocol for double data rate memories Oct 11, 2000 Issued
Array ( [id] => 1134050 [patent_doc_number] => 06792502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Microprocessor having a content addressable memory (CAM) device as a functional unit therein and method of operation' [patent_app_type] => B1 [patent_app_number] => 09/689028 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8203 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/792/06792502.pdf [firstpage_image] =>[orig_patent_app_number] => 09689028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689028
Microprocessor having a content addressable memory (CAM) device as a functional unit therein and method of operation Oct 11, 2000 Issued
Array ( [id] => 695256 [patent_doc_number] => 07076623 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-11 [patent_title] => 'Information update count managing method, information update count managing apparatus, contents usage count managing method, and content usage count storing apparatus' [patent_app_type] => utility [patent_app_number] => 09/689533 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 9191 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/076/07076623.pdf [firstpage_image] =>[orig_patent_app_number] => 09689533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689533
Information update count managing method, information update count managing apparatus, contents usage count managing method, and content usage count storing apparatus Oct 11, 2000 Issued
Array ( [id] => 7631569 [patent_doc_number] => 06665768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Table look-up operation for SIMD processors with interleaved memory systems' [patent_app_type] => B1 [patent_app_number] => 09/689099 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3123 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665768.pdf [firstpage_image] =>[orig_patent_app_number] => 09689099 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689099
Table look-up operation for SIMD processors with interleaved memory systems Oct 11, 2000 Issued
Array ( [id] => 7633090 [patent_doc_number] => 06658530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'High-performance memory module' [patent_app_type] => B1 [patent_app_number] => 09/687202 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3035 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658530.pdf [firstpage_image] =>[orig_patent_app_number] => 09687202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/687202
High-performance memory module Oct 11, 2000 Issued
Array ( [id] => 1169881 [patent_doc_number] => 06766417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Entertainment apparatus, information processing unit and portable storage device' [patent_app_type] => B1 [patent_app_number] => 09/685525 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3067 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766417.pdf [firstpage_image] =>[orig_patent_app_number] => 09685525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685525
Entertainment apparatus, information processing unit and portable storage device Oct 9, 2000 Issued
Array ( [id] => 1381648 [patent_doc_number] => 06574713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Heuristic for identifying loads guaranteed to hit in processor cache' [patent_app_type] => B1 [patent_app_number] => 09/685431 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4109 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574713.pdf [firstpage_image] =>[orig_patent_app_number] => 09685431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685431
Heuristic for identifying loads guaranteed to hit in processor cache Oct 9, 2000 Issued
Array ( [id] => 1418715 [patent_doc_number] => 06546460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Recording and/or reproducing method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/679100 [patent_app_country] => US [patent_app_date] => 2000-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6773 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546460.pdf [firstpage_image] =>[orig_patent_app_number] => 09679100 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679100
Recording and/or reproducing method and apparatus Oct 3, 2000 Issued
Array ( [id] => 1185767 [patent_doc_number] => 06745277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Intelligent interleaving scheme for multibank memory' [patent_app_type] => B1 [patent_app_number] => 09/679266 [patent_app_country] => US [patent_app_date] => 2000-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4332 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745277.pdf [firstpage_image] =>[orig_patent_app_number] => 09679266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679266
Intelligent interleaving scheme for multibank memory Oct 3, 2000 Issued
Array ( [id] => 774147 [patent_doc_number] => 07007151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-28 [patent_title] => 'System, device, and method for controlling access to a memory' [patent_app_type] => utility [patent_app_number] => 09/679461 [patent_app_country] => US [patent_app_date] => 2000-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5418 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/007/07007151.pdf [firstpage_image] =>[orig_patent_app_number] => 09679461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679461
System, device, and method for controlling access to a memory Oct 3, 2000 Issued
Array ( [id] => 1406830 [patent_doc_number] => 06560687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method of implementing a translation lookaside buffer with support for a real space control' [patent_app_type] => B1 [patent_app_number] => 09/677345 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2402 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560687.pdf [firstpage_image] =>[orig_patent_app_number] => 09677345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677345
Method of implementing a translation lookaside buffer with support for a real space control Oct 1, 2000 Issued
Array ( [id] => 1185780 [patent_doc_number] => 06745284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Data storage subsystem including a storage disk array employing dynamic data striping' [patent_app_type] => B1 [patent_app_number] => 09/678466 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5442 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745284.pdf [firstpage_image] =>[orig_patent_app_number] => 09678466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/678466
Data storage subsystem including a storage disk array employing dynamic data striping Oct 1, 2000 Issued
Array ( [id] => 1432396 [patent_doc_number] => 06505288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Matrix operation apparatus and digital signal processor capable of performing matrix operations' [patent_app_type] => B1 [patent_app_number] => 09/638951 [patent_app_country] => US [patent_app_date] => 2000-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 4671 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505288.pdf [firstpage_image] =>[orig_patent_app_number] => 09638951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638951
Matrix operation apparatus and digital signal processor capable of performing matrix operations Aug 15, 2000 Issued
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