
Midys Rojas
Examiner (ID: 17339, Phone: (571)272-4207 , Office: P/2133 )
| Most Active Art Unit | 2133 |
| Art Unit(s) | 2185, 2188, 2133, 2189 |
| Total Applications | 1097 |
| Issued Applications | 926 |
| Pending Applications | 57 |
| Abandoned Applications | 132 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20474731
[patent_doc_number] => 20260016952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-15
[patent_title] => KV CACHE BLOCK-QUANTIZATION ORIENTED DATA HANDLING
[patent_app_type] => utility
[patent_app_number] => 18/772712
[patent_app_country] => US
[patent_app_date] => 2024-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7845
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772712
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/772712 | KV cache block-quantization oriented data handling | Jul 14, 2024 | Issued |
Array
(
[id] => 20434208
[patent_doc_number] => 12504889
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-23
[patent_title] => Memory management method for evenly distributing input output latency time, memory storage device, and memory control circuit unit
[patent_app_type] => utility
[patent_app_number] => 18/760043
[patent_app_country] => US
[patent_app_date] => 2024-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2133
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 358
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760043
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/760043 | Memory management method for evenly distributing input output latency time, memory storage device, and memory control circuit unit | Jun 30, 2024 | Issued |
| 18/724303 | CACHE, CACHE MANAGEMENT METHOD AND ELECTRONIC DEVICE | Jun 25, 2024 | Pending |
Array
(
[id] => 19878386
[patent_doc_number] => 20250110643
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-03
[patent_title] => APPARATUSES AND METHODS FOR BOUNDED FAULT COMPLIANT METADATA STORAGE
[patent_app_type] => utility
[patent_app_number] => 18/747658
[patent_app_country] => US
[patent_app_date] => 2024-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10027
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747658
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/747658 | APPARATUSES AND METHODS FOR BOUNDED FAULT COMPLIANT METADATA STORAGE | Jun 18, 2024 | Pending |
Array
(
[id] => 19466240
[patent_doc_number] => 20240319910
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => Alleviating Interconnect Traffic in a Disaggregated Memory System
[patent_app_type] => utility
[patent_app_number] => 18/731056
[patent_app_country] => US
[patent_app_date] => 2024-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10170
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731056
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/731056 | Alleviating Interconnect Traffic in a Disaggregated Memory System | May 30, 2024 | Abandoned |
Array
(
[id] => 19466241
[patent_doc_number] => 20240319911
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => Alleviating Interconnect Traffic in a Disaggregated Memory System
[patent_app_type] => utility
[patent_app_number] => 18/731089
[patent_app_country] => US
[patent_app_date] => 2024-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10170
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731089
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/731089 | Alleviating interconnect traffic in a disaggregated memory system | May 30, 2024 | Issued |
Array
(
[id] => 19450905
[patent_doc_number] => 20240311035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => MECHANISMS FOR GROUPING NODES
[patent_app_type] => utility
[patent_app_number] => 18/670065
[patent_app_country] => US
[patent_app_date] => 2024-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12045
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670065
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/670065 | Mechanisms for grouping nodes | May 20, 2024 | Issued |
Array
(
[id] => 19434460
[patent_doc_number] => 20240302958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => MEMORY MANAGEMENT
[patent_app_type] => utility
[patent_app_number] => 18/657466
[patent_app_country] => US
[patent_app_date] => 2024-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9955
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657466
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/657466 | Memory management | May 6, 2024 | Issued |
Array
(
[id] => 20188524
[patent_doc_number] => 12399636
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-26
[patent_title] => Multi-modal refresh of dynamic, random-access memory
[patent_app_type] => utility
[patent_app_number] => 18/655510
[patent_app_country] => US
[patent_app_date] => 2024-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655510
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/655510 | Multi-modal refresh of dynamic, random-access memory | May 5, 2024 | Issued |
Array
(
[id] => 20051906
[patent_doc_number] => 20250190128
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-12
[patent_title] => CONTROLLER AND STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/651371
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2376
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651371
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/651371 | CONTROLLER AND STORAGE DEVICE | Apr 29, 2024 | Pending |
Array
(
[id] => 19382943
[patent_doc_number] => 20240272813
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => Computing System And Transposition Method Therefor
[patent_app_type] => utility
[patent_app_number] => 18/641623
[patent_app_country] => US
[patent_app_date] => 2024-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5044
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641623
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/641623 | Computing system and transposition method therefor | Apr 21, 2024 | Issued |
Array
(
[id] => 20061458
[patent_doc_number] => 20250199680
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => CONTROLLER, STORAGE DEVICE, HOST DEVICE AND COMPUTING SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/624729
[patent_app_country] => US
[patent_app_date] => 2024-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2400
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624729
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/624729 | CONTROLLER, STORAGE DEVICE, HOST DEVICE AND COMPUTING SYSTEM | Apr 1, 2024 | Pending |
Array
(
[id] => 19303097
[patent_doc_number] => 20240231676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE VOLTAGE
[patent_app_type] => utility
[patent_app_number] => 18/616006
[patent_app_country] => US
[patent_app_date] => 2024-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13848
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616006
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/616006 | Voltage bin calibration based on a voltage distribution reference voltage | Mar 24, 2024 | Issued |
Array
(
[id] => 19466201
[patent_doc_number] => 20240319871
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => MEMORY DEVICE USING MULTISTAGE ACCELERATION, OPERATING METHOD OF MEMORY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/614368
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10883
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614368
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614368 | MEMORY DEVICE USING MULTISTAGE ACCELERATION, OPERATING METHOD OF MEMORY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME | Mar 21, 2024 | Pending |
Array
(
[id] => 19719236
[patent_doc_number] => 12204775
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2025-01-21
[patent_title] => Storage system and a method of controlling energy consumption therein
[patent_app_type] => utility
[patent_app_number] => 18/609786
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 28
[patent_no_of_words] => 24035
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609786
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/609786 | Storage system and a method of controlling energy consumption therein | Mar 18, 2024 | Issued |
Array
(
[id] => 19756403
[patent_doc_number] => 20250044968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-06
[patent_title] => STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/602472
[patent_app_country] => US
[patent_app_date] => 2024-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7754
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602472
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/602472 | Storage device | Mar 11, 2024 | Issued |
Array
(
[id] => 19963672
[patent_doc_number] => 12333181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-17
[patent_title] => Source address memory managment
[patent_app_type] => utility
[patent_app_number] => 18/600269
[patent_app_country] => US
[patent_app_date] => 2024-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4943
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600269
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/600269 | Source address memory managment | Mar 7, 2024 | Issued |
Array
(
[id] => 20265708
[patent_doc_number] => 12436699
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-07
[patent_title] => Integrated circuit data stream processing using paged buffering
[patent_app_type] => utility
[patent_app_number] => 18/589430
[patent_app_country] => US
[patent_app_date] => 2024-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7084
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589430
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/589430 | Integrated circuit data stream processing using paged buffering | Feb 27, 2024 | Issued |
Array
(
[id] => 19481825
[patent_doc_number] => 20240329867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => APPARATUS WITH MEMORY CELL CALIBRATION MECHANISM AND METHODS FOR OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/584993
[patent_app_country] => US
[patent_app_date] => 2024-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7163
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584993
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/584993 | Apparatus with memory cell calibration mechanism and methods for operating the same | Feb 21, 2024 | Issued |
Array
(
[id] => 19925028
[patent_doc_number] => 12299310
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Methods and systems to interface between a multi-site distributed storage system and an external mediator to efficiently process events related to continuity
[patent_app_type] => utility
[patent_app_number] => 18/429911
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5930
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429911
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/429911 | Methods and systems to interface between a multi-site distributed storage system and an external mediator to efficiently process events related to continuity | Jan 31, 2024 | Issued |