Mikado Ryan Buiz
Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )
Most Active Art Unit | 3506 |
Art Unit(s) | 3731, 2899, 3506 |
Total Applications | 2305 |
Issued Applications | 2195 |
Pending Applications | 18 |
Abandoned Applications | 92 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4476932
[patent_doc_number] => 07868335
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[patent_issue_date] => 2011-01-11
[patent_title] => 'Modulation doped super-lattice sub-collector for high-performance HBTs and BJTs'
[patent_app_type] => utility
[patent_app_number] => 12/193436
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/193436 | Modulation doped super-lattice sub-collector for high-performance HBTs and BJTs | Aug 17, 2008 | Issued |
Array
(
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[patent_issue_date] => 2010-02-18
[patent_title] => 'Shallow Trench Isolation'
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[patent_app_date] => 2008-08-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/192626 | Shallow trench isolation | Aug 14, 2008 | Issued |
Array
(
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[patent_doc_number] => 20100038683
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[patent_kind] => A1
[patent_issue_date] => 2010-02-18
[patent_title] => 'INTEGRATED CIRCUIT MODELING, DESIGN, AND FABRICATION BASED ON DEGRADATION MECHANISMS'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/192850 | Integrated circuit modeling, design, and fabrication based on degradation mechanisms | Aug 14, 2008 | Issued |
Array
(
[id] => 7763592
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[patent_kind] => B2
[patent_issue_date] => 2012-02-14
[patent_title] => 'Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof'
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Array
(
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[patent_issue_date] => 2009-06-04
[patent_title] => 'SOLIDE-STATE LIGHT SOURCE'
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Array
(
[id] => 4536421
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Array
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[patent_title] => 'Selective deposition of amorphous silicon films on metal gates'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/228615 | Selective deposition of amorphous silicon films on metal gates | Aug 13, 2008 | Issued |
Array
(
[id] => 326505
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[patent_issue_date] => 2009-04-07
[patent_title] => 'Aligning stacked chips using resistance assistance'
[patent_app_type] => utility
[patent_app_number] => 12/190395
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/190395 | Aligning stacked chips using resistance assistance | Aug 11, 2008 | Issued |
Array
(
[id] => 4576405
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/187525 | Avalanche photodiode | Aug 6, 2008 | Issued |
Array
(
[id] => 6606532
[patent_doc_number] => 20100033273
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[patent_title] => 'Coupler Structure'
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Array
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[id] => 6600033
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[patent_title] => 'LDMOS DEVICE FOR ESD PROTECTION CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/186716 | LDMOS device for ESD protection circuit | Aug 5, 2008 | Issued |
Array
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[id] => 4574504
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Array
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Array
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Array
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Array
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Array
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Array
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