Search

Mikado Ryan Buiz

Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )

Most Active Art Unit
3506
Art Unit(s)
3731, 2899, 3506
Total Applications
2305
Issued Applications
2195
Pending Applications
18
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 363440 [patent_doc_number] => 07482251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'Etch before grind for semiconductor die singulation' [patent_app_type] => utility [patent_app_number] => 11/891392 [patent_app_country] => US [patent_app_date] => 2007-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3450 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482251.pdf [firstpage_image] =>[orig_patent_app_number] => 11891392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/891392
Etch before grind for semiconductor die singulation Aug 8, 2007 Issued
Array ( [id] => 5010958 [patent_doc_number] => 20070281437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Image sensor applied with device isolation technique for reducing dark signals and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/890991 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2524 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20070281437.pdf [firstpage_image] =>[orig_patent_app_number] => 11890991 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/890991
Image sensor applied with device isolation technique for reducing dark signals and fabrication method thereof Aug 7, 2007 Issued
Array ( [id] => 337989 [patent_doc_number] => 07504330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Method of forming an insulative film' [patent_app_type] => utility [patent_app_number] => 11/882791 [patent_app_country] => US [patent_app_date] => 2007-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6156 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/504/07504330.pdf [firstpage_image] =>[orig_patent_app_number] => 11882791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/882791
Method of forming an insulative film Aug 5, 2007 Issued
Array ( [id] => 5416495 [patent_doc_number] => 20090042382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'Device packages' [patent_app_type] => utility [patent_app_number] => 11/890342 [patent_app_country] => US [patent_app_date] => 2007-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3923 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20090042382.pdf [firstpage_image] =>[orig_patent_app_number] => 11890342 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/890342
Device packages Aug 5, 2007 Abandoned
Array ( [id] => 160217 [patent_doc_number] => 07675170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Removable wafer expander for die bonding equipment' [patent_app_type] => utility [patent_app_number] => 11/833605 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1516 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/675/07675170.pdf [firstpage_image] =>[orig_patent_app_number] => 11833605 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833605
Removable wafer expander for die bonding equipment Aug 2, 2007 Issued
Array ( [id] => 250791 [patent_doc_number] => 07582547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Method for junction formation in a semiconductor device and the semiconductor device made thereof' [patent_app_type] => utility [patent_app_number] => 11/833931 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4832 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/582/07582547.pdf [firstpage_image] =>[orig_patent_app_number] => 11833931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833931
Method for junction formation in a semiconductor device and the semiconductor device made thereof Aug 2, 2007 Issued
Array ( [id] => 5358155 [patent_doc_number] => 20090032949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Method of depositing Tungsten using plasma-treated tungsten nitride' [patent_app_type] => utility [patent_app_number] => 11/890192 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4990 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20090032949.pdf [firstpage_image] =>[orig_patent_app_number] => 11890192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/890192
Method of depositing Tungsten using plasma-treated tungsten nitride Aug 1, 2007 Abandoned
Array ( [id] => 4803126 [patent_doc_number] => 20080014714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'METHOD OF FABRICATING A HYBRID SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 11/832431 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9597 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014714.pdf [firstpage_image] =>[orig_patent_app_number] => 11832431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/832431
Method of fabricating a hybrid substrate Jul 31, 2007 Issued
Array ( [id] => 5361160 [patent_doc_number] => 20090035954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'INTERCONNECT STRUCTURE WITH GRAIN GROWTH PROMOTION LAYER AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/831149 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1779 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20090035954.pdf [firstpage_image] =>[orig_patent_app_number] => 11831149 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831149
Interconnect structure with grain growth promotion layer and method for forming the same Jul 30, 2007 Issued
Array ( [id] => 299786 [patent_doc_number] => 07537985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Double gate isolation' [patent_app_type] => utility [patent_app_number] => 11/830872 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 5240 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/537/07537985.pdf [firstpage_image] =>[orig_patent_app_number] => 11830872 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830872
Double gate isolation Jul 30, 2007 Issued
Array ( [id] => 6250765 [patent_doc_number] => 20100027946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'STACKABLE OPTOELECTRONICS CHIP-TO-CHIP INTERCONNECTS AND METHOD OF MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 11/830864 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 61 [patent_no_of_words] => 17856 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20100027946.pdf [firstpage_image] =>[orig_patent_app_number] => 11830864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830864
Stackable optoelectronics chip-to-chip interconnects and method of manufacturing Jul 30, 2007 Issued
Array ( [id] => 267050 [patent_doc_number] => 07566575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Mounting circuit and method for producing semiconductor-chip-mounting circuit' [patent_app_type] => utility [patent_app_number] => 11/888121 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5898 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/566/07566575.pdf [firstpage_image] =>[orig_patent_app_number] => 11888121 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/888121
Mounting circuit and method for producing semiconductor-chip-mounting circuit Jul 29, 2007 Issued
Array ( [id] => 589046 [patent_doc_number] => 07435628 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-14 [patent_title] => 'Method of forming a vertical MOS transistor' [patent_app_type] => utility [patent_app_number] => 11/881671 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/435/07435628.pdf [firstpage_image] =>[orig_patent_app_number] => 11881671 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/881671
Method of forming a vertical MOS transistor Jul 26, 2007 Issued
Array ( [id] => 5521535 [patent_doc_number] => 20090029516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'METHOD TO IMPROVE TRANSISTOR TOX USING HIGH-ANGLE IMPLANTS WITH NO ADDITIONAL MASKS' [patent_app_type] => utility [patent_app_number] => 11/829181 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20090029516.pdf [firstpage_image] =>[orig_patent_app_number] => 11829181 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/829181
Method to improve transistor Tox using high-angle implants with no additional masks Jul 26, 2007 Issued
Array ( [id] => 4731123 [patent_doc_number] => 20080048208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/828855 [patent_app_country] => US [patent_app_date] => 2007-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4211 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048208.pdf [firstpage_image] =>[orig_patent_app_number] => 11828855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/828855
Electrostatic discharge protection device for an integrated circuit Jul 25, 2007 Issued
Array ( [id] => 220934 [patent_doc_number] => 07608480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion' [patent_app_type] => utility [patent_app_number] => 11/880162 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7011 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/608/07608480.pdf [firstpage_image] =>[orig_patent_app_number] => 11880162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/880162
Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion Jul 19, 2007 Issued
Array ( [id] => 4907152 [patent_doc_number] => 20080017918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'THREE-DIMENSIONAL FLASH MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 11/781001 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20080017918.pdf [firstpage_image] =>[orig_patent_app_number] => 11781001 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/781001
Three-dimensional flash memory cell Jul 19, 2007 Issued
Array ( [id] => 5016282 [patent_doc_number] => 20070259491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/826251 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10989 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20070259491.pdf [firstpage_image] =>[orig_patent_app_number] => 11826251 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/826251
Semiconductor device and method for fabricating the same Jul 12, 2007 Issued
Array ( [id] => 4813453 [patent_doc_number] => 20080194084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'METHOD OF FABRICATION OF HIGHLY HEAT DISSIPATIVE SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 11/774201 [patent_app_country] => US [patent_app_date] => 2007-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3544 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20080194084.pdf [firstpage_image] =>[orig_patent_app_number] => 11774201 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774201
Method of fabrication of highly heat dissipative substrates Jul 5, 2007 Issued
Array ( [id] => 5293785 [patent_doc_number] => 20090008711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Fully Isolated High-Voltage MOS Device' [patent_app_type] => utility [patent_app_number] => 11/773365 [patent_app_country] => US [patent_app_date] => 2007-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20090008711.pdf [firstpage_image] =>[orig_patent_app_number] => 11773365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/773365
Fully isolated high-voltage MOS device Jul 2, 2007 Issued
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