Mikado Ryan Buiz
Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )
Most Active Art Unit | 3506 |
Art Unit(s) | 3731, 2899, 3506 |
Total Applications | 2305 |
Issued Applications | 2195 |
Pending Applications | 18 |
Abandoned Applications | 92 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 363440
[patent_doc_number] => 07482251
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[patent_issue_date] => 2009-01-27
[patent_title] => 'Etch before grind for semiconductor die singulation'
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[patent_app_number] => 11/891392
[patent_app_country] => US
[patent_app_date] => 2007-08-09
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[pdf_file] => patents/07/482/07482251.pdf
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Array
(
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[patent_doc_number] => 20070281437
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[patent_kind] => A1
[patent_issue_date] => 2007-12-06
[patent_title] => 'Image sensor applied with device isolation technique for reducing dark signals and fabrication method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/890991 | Image sensor applied with device isolation technique for reducing dark signals and fabrication method thereof | Aug 7, 2007 | Issued |
Array
(
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[patent_title] => 'Method of forming an insulative film'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/882791 | Method of forming an insulative film | Aug 5, 2007 | Issued |
Array
(
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[patent_title] => 'Device packages'
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[patent_app_number] => 11/890342
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/890342 | Device packages | Aug 5, 2007 | Abandoned |
Array
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Array
(
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[patent_title] => 'Method for junction formation in a semiconductor device and the semiconductor device made thereof'
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Array
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[id] => 5358155
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[patent_title] => 'Method of depositing Tungsten using plasma-treated tungsten nitride'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/890192 | Method of depositing Tungsten using plasma-treated tungsten nitride | Aug 1, 2007 | Abandoned |
Array
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[id] => 4803126
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[patent_issue_date] => 2008-01-17
[patent_title] => 'METHOD OF FABRICATING A HYBRID SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 11/832431
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/832431 | Method of fabricating a hybrid substrate | Jul 31, 2007 | Issued |
Array
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[id] => 5361160
[patent_doc_number] => 20090035954
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[patent_issue_date] => 2009-02-05
[patent_title] => 'INTERCONNECT STRUCTURE WITH GRAIN GROWTH PROMOTION LAYER AND METHOD FOR FORMING THE SAME'
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[patent_app_number] => 11/831149
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/831149 | Interconnect structure with grain growth promotion layer and method for forming the same | Jul 30, 2007 | Issued |
Array
(
[id] => 299786
[patent_doc_number] => 07537985
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[patent_title] => 'Double gate isolation'
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Array
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[id] => 6250765
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Array
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[id] => 267050
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Array
(
[id] => 589046
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[patent_title] => 'Method of forming a vertical MOS transistor'
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Array
(
[id] => 5521535
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[patent_title] => 'METHOD TO IMPROVE TRANSISTOR TOX USING HIGH-ANGLE IMPLANTS WITH NO ADDITIONAL MASKS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/829181 | Method to improve transistor Tox using high-angle implants with no additional masks | Jul 26, 2007 | Issued |
Array
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[patent_title] => 'ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR AN INTEGRATED CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/828855 | Electrostatic discharge protection device for an integrated circuit | Jul 25, 2007 | Issued |
Array
(
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Array
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[patent_title] => 'THREE-DIMENSIONAL FLASH MEMORY CELL'
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Array
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Array
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Array
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