Mikado Ryan Buiz
Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )
Most Active Art Unit | 3506 |
Art Unit(s) | 3731, 2899, 3506 |
Total Applications | 2305 |
Issued Applications | 2195 |
Pending Applications | 18 |
Abandoned Applications | 92 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 270482
[patent_doc_number] => 07563718
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-21
[patent_title] => 'Method for forming tungsten layer of semiconductor device and method for forming tungsten wiring layer using the same'
[patent_app_type] => utility
[patent_app_number] => 11/618631
[patent_app_country] => US
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[pdf_file] => patents/07/563/07563718.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618631 | Method for forming tungsten layer of semiconductor device and method for forming tungsten wiring layer using the same | Dec 28, 2006 | Issued |
Array
(
[id] => 299810
[patent_doc_number] => 07538009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-26
[patent_title] => 'Method for fabricating STI gap fill oxide layer in semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/616305
[patent_app_country] => US
[patent_app_date] => 2006-12-27
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[pdf_file] => patents/07/538/07538009.pdf
[firstpage_image] =>[orig_patent_app_number] => 11616305
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616305 | Method for fabricating STI gap fill oxide layer in semiconductor devices | Dec 26, 2006 | Issued |
Array
(
[id] => 4752679
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[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'METHOD FOR FABRICATING A MICROELECTRONIC CONDUCTOR STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 11/616532
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[pdf_file] => publications/A1/0160/20080160754.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616532 | METHOD FOR FABRICATING A MICROELECTRONIC CONDUCTOR STRUCTURE | Dec 26, 2006 | Abandoned |
Array
(
[id] => 4866971
[patent_doc_number] => 20080146030
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-19
[patent_title] => 'SYSTEM AND METHOD FOR DIRECT ETCHING'
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[patent_app_number] => 11/615972
[patent_app_country] => US
[patent_app_date] => 2006-12-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615972 | System and method for direct etching | Dec 22, 2006 | Issued |
Array
(
[id] => 5023001
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[patent_issue_date] => 2007-06-28
[patent_title] => 'Method for Manufacturing Semiconductor Device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615105 | Method for manufacturing semiconductor device | Dec 21, 2006 | Issued |
Array
(
[id] => 4879913
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[patent_title] => 'METHOD OF FORMATION OF A DAMASCENE STRUCTURE UTILIZING A PROTECTIVE FILM'
[patent_app_type] => utility
[patent_app_number] => 11/615272
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[firstpage_image] =>[orig_patent_app_number] => 11615272
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615272 | Method of formation of a damascene structure utilizing a protective film | Dec 21, 2006 | Issued |
Array
(
[id] => 256325
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[patent_title] => 'Semiconductor device and metal line fabrication method of the same'
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[pdf_file] => patents/07/575/07575998.pdf
[firstpage_image] =>[orig_patent_app_number] => 11615661
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615661 | Semiconductor device and metal line fabrication method of the same | Dec 21, 2006 | Issued |
Array
(
[id] => 337992
[patent_doc_number] => 07504333
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[patent_issue_date] => 2009-03-17
[patent_title] => 'Method of forming bit line of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/614082
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11614082
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/614082 | Method of forming bit line of semiconductor device | Dec 20, 2006 | Issued |
Array
(
[id] => 267133
[patent_doc_number] => 07566658
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[patent_issue_date] => 2009-07-28
[patent_title] => 'Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device'
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[patent_app_number] => 11/613815
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/613815 | Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device | Dec 19, 2006 | Issued |
Array
(
[id] => 4938922
[patent_doc_number] => 20080076241
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[patent_issue_date] => 2008-03-27
[patent_title] => 'Method for reducing stress between a conductive layer and a mask layer and use of the same'
[patent_app_type] => utility
[patent_app_number] => 11/641131
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/641131 | Method for reducing stress between a conductive layer and a mask layer and use of the same | Dec 18, 2006 | Abandoned |
Array
(
[id] => 243275
[patent_doc_number] => 07589009
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[patent_issue_date] => 2009-09-15
[patent_title] => 'Method for fabricating a top conductive layer in a semiconductor die and related structure'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/641925 | Method for fabricating a top conductive layer in a semiconductor die and related structure | Dec 17, 2006 | Issued |
Array
(
[id] => 4864320
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[patent_issue_date] => 2008-06-19
[patent_title] => 'REPROGRAMMABLE CIRCUIT BOARD WITH ALIGNMENT-INSENSITIVE SUPPORT FOR MULTIPLE COMPONENT CONTACT TYPES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/611263 | Reprogrammable circuit board with alignment-insensitive support for multiple component contact types | Dec 14, 2006 | Issued |
Array
(
[id] => 5031562
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[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE'
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[firstpage_image] =>[orig_patent_app_number] => 11608593
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/608593 | Method of manufacturing semiconductor light emitting device | Dec 7, 2006 | Issued |
Array
(
[id] => 5019631
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[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
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Array
(
[id] => 4988830
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/566034 | Method of fabricating a thin film and metal wiring in a semiconductor device | Nov 30, 2006 | Issued |
Array
(
[id] => 5282354
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Array
(
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Array
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Array
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Array
(
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[patent_title] => 'Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement'
[patent_app_type] => utility
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