Search

Mikado Ryan Buiz

Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )

Most Active Art Unit
3506
Art Unit(s)
3731, 2899, 3506
Total Applications
2305
Issued Applications
2195
Pending Applications
18
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 270482 [patent_doc_number] => 07563718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Method for forming tungsten layer of semiconductor device and method for forming tungsten wiring layer using the same' [patent_app_type] => utility [patent_app_number] => 11/618631 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1707 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/563/07563718.pdf [firstpage_image] =>[orig_patent_app_number] => 11618631 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618631
Method for forming tungsten layer of semiconductor device and method for forming tungsten wiring layer using the same Dec 28, 2006 Issued
Array ( [id] => 299810 [patent_doc_number] => 07538009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Method for fabricating STI gap fill oxide layer in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/616305 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1894 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538009.pdf [firstpage_image] =>[orig_patent_app_number] => 11616305 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616305
Method for fabricating STI gap fill oxide layer in semiconductor devices Dec 26, 2006 Issued
Array ( [id] => 4752679 [patent_doc_number] => 20080160754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD FOR FABRICATING A MICROELECTRONIC CONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/616532 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3899 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20080160754.pdf [firstpage_image] =>[orig_patent_app_number] => 11616532 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616532
METHOD FOR FABRICATING A MICROELECTRONIC CONDUCTOR STRUCTURE Dec 26, 2006 Abandoned
Array ( [id] => 4866971 [patent_doc_number] => 20080146030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'SYSTEM AND METHOD FOR DIRECT ETCHING' [patent_app_type] => utility [patent_app_number] => 11/615972 [patent_app_country] => US [patent_app_date] => 2006-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4680 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20080146030.pdf [firstpage_image] =>[orig_patent_app_number] => 11615972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615972
System and method for direct etching Dec 22, 2006 Issued
Array ( [id] => 5023001 [patent_doc_number] => 20070148967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method for Manufacturing Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 11/615105 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148967.pdf [firstpage_image] =>[orig_patent_app_number] => 11615105 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615105
Method for manufacturing semiconductor device Dec 21, 2006 Issued
Array ( [id] => 4879913 [patent_doc_number] => 20080153296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'METHOD OF FORMATION OF A DAMASCENE STRUCTURE UTILIZING A PROTECTIVE FILM' [patent_app_type] => utility [patent_app_number] => 11/615272 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153296.pdf [firstpage_image] =>[orig_patent_app_number] => 11615272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615272
Method of formation of a damascene structure utilizing a protective film Dec 21, 2006 Issued
Array ( [id] => 256325 [patent_doc_number] => 07575998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Semiconductor device and metal line fabrication method of the same' [patent_app_type] => utility [patent_app_number] => 11/615661 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2548 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/575/07575998.pdf [firstpage_image] =>[orig_patent_app_number] => 11615661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615661
Semiconductor device and metal line fabrication method of the same Dec 21, 2006 Issued
Array ( [id] => 337992 [patent_doc_number] => 07504333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Method of forming bit line of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/614082 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1749 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/504/07504333.pdf [firstpage_image] =>[orig_patent_app_number] => 11614082 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614082
Method of forming bit line of semiconductor device Dec 20, 2006 Issued
Array ( [id] => 267133 [patent_doc_number] => 07566658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/613815 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2021 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/566/07566658.pdf [firstpage_image] =>[orig_patent_app_number] => 11613815 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613815
Method for fabricating a metal interconnection using a dual damascene process and resulting semiconductor device Dec 19, 2006 Issued
Array ( [id] => 4938922 [patent_doc_number] => 20080076241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Method for reducing stress between a conductive layer and a mask layer and use of the same' [patent_app_type] => utility [patent_app_number] => 11/641131 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20080076241.pdf [firstpage_image] =>[orig_patent_app_number] => 11641131 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/641131
Method for reducing stress between a conductive layer and a mask layer and use of the same Dec 18, 2006 Abandoned
Array ( [id] => 243275 [patent_doc_number] => 07589009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method for fabricating a top conductive layer in a semiconductor die and related structure' [patent_app_type] => utility [patent_app_number] => 11/641925 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589009.pdf [firstpage_image] =>[orig_patent_app_number] => 11641925 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/641925
Method for fabricating a top conductive layer in a semiconductor die and related structure Dec 17, 2006 Issued
Array ( [id] => 4864320 [patent_doc_number] => 20080143379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'REPROGRAMMABLE CIRCUIT BOARD WITH ALIGNMENT-INSENSITIVE SUPPORT FOR MULTIPLE COMPONENT CONTACT TYPES' [patent_app_type] => utility [patent_app_number] => 11/611263 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 50325 [patent_no_of_claims] => 120 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20080143379.pdf [firstpage_image] =>[orig_patent_app_number] => 11611263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/611263
Reprogrammable circuit board with alignment-insensitive support for multiple component contact types Dec 14, 2006 Issued
Array ( [id] => 5031562 [patent_doc_number] => 20070096101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 11/608593 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4225 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096101.pdf [firstpage_image] =>[orig_patent_app_number] => 11608593 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608593
Method of manufacturing semiconductor light emitting device Dec 7, 2006 Issued
Array ( [id] => 5019631 [patent_doc_number] => 20070145597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/567681 [patent_app_country] => US [patent_app_date] => 2006-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145597.pdf [firstpage_image] =>[orig_patent_app_number] => 11567681 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/567681
Semiconductor device and method for manufacturing the same Dec 5, 2006 Issued
Array ( [id] => 4988830 [patent_doc_number] => 20070155169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'METHOD OF FABRICATING A THIN FILM AND METAL WIRING IN A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/566034 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2588 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20070155169.pdf [firstpage_image] =>[orig_patent_app_number] => 11566034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/566034
Method of fabricating a thin film and metal wiring in a semiconductor device Nov 30, 2006 Issued
Array ( [id] => 5282354 [patent_doc_number] => 20090096028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'Transistor of the I-MOS Type Comprising Two Independent Gates and Method of Using Such a Transistor' [patent_app_type] => utility [patent_app_number] => 12/085866 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2459 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20090096028.pdf [firstpage_image] =>[orig_patent_app_number] => 12085866 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/085866
Transistor of the I-MOS type comprising two independent gates and method of using such a transistor Nov 30, 2006 Issued
Array ( [id] => 243291 [patent_doc_number] => 07589025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Semiconductor processing' [patent_app_type] => utility [patent_app_number] => 11/607632 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6032 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589025.pdf [firstpage_image] =>[orig_patent_app_number] => 11607632 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607632
Semiconductor processing Nov 30, 2006 Issued
Array ( [id] => 91853 [patent_doc_number] => 07736928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Precision printing electroplating through plating mask on a solar cell substrate' [patent_app_type] => utility [patent_app_number] => 11/566205 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 14558 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/736/07736928.pdf [firstpage_image] =>[orig_patent_app_number] => 11566205 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/566205
Precision printing electroplating through plating mask on a solar cell substrate Nov 30, 2006 Issued
Array ( [id] => 5040771 [patent_doc_number] => 20070093053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'METHOD OF FABRICATING INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/565632 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2566 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20070093053.pdf [firstpage_image] =>[orig_patent_app_number] => 11565632 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565632
Method of fabricating interconnect structure Nov 30, 2006 Issued
Array ( [id] => 6327440 [patent_doc_number] => 20100327291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement' [patent_app_type] => utility [patent_app_number] => 11/606783 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14510 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20100327291.pdf [firstpage_image] =>[orig_patent_app_number] => 11606783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/606783
Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement Nov 29, 2006 Issued
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