Search

Mikado Ryan Buiz

Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )

Most Active Art Unit
3506
Art Unit(s)
3731, 2899, 3506
Total Applications
2305
Issued Applications
2195
Pending Applications
18
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 369839 [patent_doc_number] => 07476612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/564131 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1604 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/476/07476612.pdf [firstpage_image] =>[orig_patent_app_number] => 11564131 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/564131
Method for manufacturing semiconductor device Nov 27, 2006 Issued
Array ( [id] => 352540 [patent_doc_number] => 07491561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Pixel sensor having doped isolation structure sidewall' [patent_app_type] => utility [patent_app_number] => 11/563531 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4799 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/491/07491561.pdf [firstpage_image] =>[orig_patent_app_number] => 11563531 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563531
Pixel sensor having doped isolation structure sidewall Nov 26, 2006 Issued
Array ( [id] => 359681 [patent_doc_number] => 07485560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method for fabricating crystalline silicon thin films' [patent_app_type] => utility [patent_app_number] => 11/603043 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485560.pdf [firstpage_image] =>[orig_patent_app_number] => 11603043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/603043
Method for fabricating crystalline silicon thin films Nov 21, 2006 Issued
Array ( [id] => 303552 [patent_doc_number] => 07534689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Stress enhanced MOS transistor and methods for its fabrication' [patent_app_type] => utility [patent_app_number] => 11/562209 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/534/07534689.pdf [firstpage_image] =>[orig_patent_app_number] => 11562209 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562209
Stress enhanced MOS transistor and methods for its fabrication Nov 20, 2006 Issued
Array ( [id] => 307391 [patent_doc_number] => 07531457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Method of fabricating suspended structure' [patent_app_type] => utility [patent_app_number] => 11/561902 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2049 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531457.pdf [firstpage_image] =>[orig_patent_app_number] => 11561902 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561902
Method of fabricating suspended structure Nov 20, 2006 Issued
Array ( [id] => 5095672 [patent_doc_number] => 20070117281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Method for Manufacturing Bonded Substrate and Bonded Substrate Manufactured by the Method' [patent_app_type] => utility [patent_app_number] => 11/562162 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8098 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117281.pdf [firstpage_image] =>[orig_patent_app_number] => 11562162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562162
Method for manufacturing bonded substrate and bonded substrate manufactured by the method Nov 20, 2006 Issued
Array ( [id] => 4899432 [patent_doc_number] => 20080119046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'METHOD OF MAKING A CONTACT ON A BACKSIDE OF A DIE' [patent_app_type] => utility [patent_app_number] => 11/562161 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20080119046.pdf [firstpage_image] =>[orig_patent_app_number] => 11562161 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562161
Method of making a contact on a backside of a die Nov 20, 2006 Issued
Array ( [id] => 217010 [patent_doc_number] => 07611920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-03 [patent_title] => 'Photonic coupling scheme for photodetectors' [patent_app_type] => utility [patent_app_number] => 11/601223 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1082 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/611/07611920.pdf [firstpage_image] =>[orig_patent_app_number] => 11601223 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/601223
Photonic coupling scheme for photodetectors Nov 16, 2006 Issued
Array ( [id] => 239550 [patent_doc_number] => 07592267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Method for manufacturing semiconductor silicon substrate and apparatus for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/600105 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9874 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592267.pdf [firstpage_image] =>[orig_patent_app_number] => 11600105 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/600105
Method for manufacturing semiconductor silicon substrate and apparatus for manufacturing the same Nov 15, 2006 Issued
Array ( [id] => 7691970 [patent_doc_number] => 20070232063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'METHOD FOR REDUCING POLISH-INDUCED DAMAGE IN A CONTACT STRUCTURE BY FORMING A CAPPING LAYER' [patent_app_type] => utility [patent_app_number] => 11/559652 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7467 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20070232063.pdf [firstpage_image] =>[orig_patent_app_number] => 11559652 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559652
Method for reducing polish-induced damage in a contact structure by forming a capping layer Nov 13, 2006 Issued
Array ( [id] => 363451 [patent_doc_number] => 07482262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/559592 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482262.pdf [firstpage_image] =>[orig_patent_app_number] => 11559592 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559592
Method of manufacturing semiconductor device Nov 13, 2006 Issued
Array ( [id] => 4557495 [patent_doc_number] => 07838331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Method for dicing semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/598654 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 49 [patent_no_of_words] => 19630 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838331.pdf [firstpage_image] =>[orig_patent_app_number] => 11598654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/598654
Method for dicing semiconductor substrate Nov 13, 2006 Issued
Array ( [id] => 337981 [patent_doc_number] => 07504322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Growth of a semiconductor layer structure' [patent_app_type] => utility [patent_app_number] => 11/558972 [patent_app_country] => US [patent_app_date] => 2006-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 10509 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/504/07504322.pdf [firstpage_image] =>[orig_patent_app_number] => 11558972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/558972
Growth of a semiconductor layer structure Nov 12, 2006 Issued
Array ( [id] => 4901754 [patent_doc_number] => 20080111166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Removable spacer' [patent_app_type] => utility [patent_app_number] => 11/598242 [patent_app_country] => US [patent_app_date] => 2006-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2891 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111166.pdf [firstpage_image] =>[orig_patent_app_number] => 11598242 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/598242
Removable spacer Nov 9, 2006 Issued
Array ( [id] => 369827 [patent_doc_number] => 07476600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-13 [patent_title] => 'FET gate structure and fabrication process' [patent_app_type] => utility [patent_app_number] => 11/595242 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3073 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/476/07476600.pdf [firstpage_image] =>[orig_patent_app_number] => 11595242 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/595242
FET gate structure and fabrication process Nov 8, 2006 Issued
Array ( [id] => 131556 [patent_doc_number] => 07700460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Semiconductor device fabrication method and electronic device fabrication method' [patent_app_type] => utility [patent_app_number] => 11/594061 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 46 [patent_no_of_words] => 11797 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/700/07700460.pdf [firstpage_image] =>[orig_patent_app_number] => 11594061 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/594061
Semiconductor device fabrication method and electronic device fabrication method Nov 7, 2006 Issued
Array ( [id] => 4669932 [patent_doc_number] => 20080044992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Method for fabricating a recess gate in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/594072 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2418 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20080044992.pdf [firstpage_image] =>[orig_patent_app_number] => 11594072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/594072
Method for fabricating a recess gate in a semiconductor device Nov 7, 2006 Issued
Array ( [id] => 4965395 [patent_doc_number] => 20080108215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'INTEGRATED CIRCUIT INTERCONNECT LINES HAVING REDUCED LINE RESISTANCE' [patent_app_type] => utility [patent_app_number] => 11/557438 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 22732 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20080108215.pdf [firstpage_image] =>[orig_patent_app_number] => 11557438 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557438
INTEGRATED CIRCUIT INTERCONNECT LINES HAVING REDUCED LINE RESISTANCE Nov 6, 2006 Abandoned
Array ( [id] => 555686 [patent_doc_number] => 07468317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-23 [patent_title] => 'Method of forming metal line of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/593882 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1351 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/468/07468317.pdf [firstpage_image] =>[orig_patent_app_number] => 11593882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593882
Method of forming metal line of semiconductor device Nov 6, 2006 Issued
Array ( [id] => 4963157 [patent_doc_number] => 20080105977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'INTERCONNECT LAYERS WITHOUT ELECTROMIGRATION' [patent_app_type] => utility [patent_app_number] => 11/556802 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20080105977.pdf [firstpage_image] =>[orig_patent_app_number] => 11556802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556802
Interconnect layers without electromigration Nov 5, 2006 Issued
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