Mikado Ryan Buiz
Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )
Most Active Art Unit | 3506 |
Art Unit(s) | 3731, 2899, 3506 |
Total Applications | 2305 |
Issued Applications | 2195 |
Pending Applications | 18 |
Abandoned Applications | 92 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 369839
[patent_doc_number] => 07476612
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-13
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/564131
[patent_app_country] => US
[patent_app_date] => 2006-11-28
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[pdf_file] => patents/07/476/07476612.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/564131 | Method for manufacturing semiconductor device | Nov 27, 2006 | Issued |
Array
(
[id] => 352540
[patent_doc_number] => 07491561
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-17
[patent_title] => 'Pixel sensor having doped isolation structure sidewall'
[patent_app_type] => utility
[patent_app_number] => 11/563531
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/563531 | Pixel sensor having doped isolation structure sidewall | Nov 26, 2006 | Issued |
Array
(
[id] => 359681
[patent_doc_number] => 07485560
[patent_country] => US
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[patent_issue_date] => 2009-02-03
[patent_title] => 'Method for fabricating crystalline silicon thin films'
[patent_app_type] => utility
[patent_app_number] => 11/603043
[patent_app_country] => US
[patent_app_date] => 2006-11-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/603043 | Method for fabricating crystalline silicon thin films | Nov 21, 2006 | Issued |
Array
(
[id] => 303552
[patent_doc_number] => 07534689
[patent_country] => US
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[patent_issue_date] => 2009-05-19
[patent_title] => 'Stress enhanced MOS transistor and methods for its fabrication'
[patent_app_type] => utility
[patent_app_number] => 11/562209
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[patent_app_date] => 2006-11-21
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[pdf_file] => patents/07/534/07534689.pdf
[firstpage_image] =>[orig_patent_app_number] => 11562209
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/562209 | Stress enhanced MOS transistor and methods for its fabrication | Nov 20, 2006 | Issued |
Array
(
[id] => 307391
[patent_doc_number] => 07531457
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[patent_kind] => B2
[patent_issue_date] => 2009-05-12
[patent_title] => 'Method of fabricating suspended structure'
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[patent_app_number] => 11/561902
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/561902 | Method of fabricating suspended structure | Nov 20, 2006 | Issued |
Array
(
[id] => 5095672
[patent_doc_number] => 20070117281
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[patent_issue_date] => 2007-05-24
[patent_title] => 'Method for Manufacturing Bonded Substrate and Bonded Substrate Manufactured by the Method'
[patent_app_type] => utility
[patent_app_number] => 11/562162
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[firstpage_image] =>[orig_patent_app_number] => 11562162
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/562162 | Method for manufacturing bonded substrate and bonded substrate manufactured by the method | Nov 20, 2006 | Issued |
Array
(
[id] => 4899432
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[patent_issue_date] => 2008-05-22
[patent_title] => 'METHOD OF MAKING A CONTACT ON A BACKSIDE OF A DIE'
[patent_app_type] => utility
[patent_app_number] => 11/562161
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[pdf_file] => publications/A1/0119/20080119046.pdf
[firstpage_image] =>[orig_patent_app_number] => 11562161
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/562161 | Method of making a contact on a backside of a die | Nov 20, 2006 | Issued |
Array
(
[id] => 217010
[patent_doc_number] => 07611920
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[patent_kind] => B1
[patent_issue_date] => 2009-11-03
[patent_title] => 'Photonic coupling scheme for photodetectors'
[patent_app_type] => utility
[patent_app_number] => 11/601223
[patent_app_country] => US
[patent_app_date] => 2006-11-17
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[pdf_file] => patents/07/611/07611920.pdf
[firstpage_image] =>[orig_patent_app_number] => 11601223
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/601223 | Photonic coupling scheme for photodetectors | Nov 16, 2006 | Issued |
Array
(
[id] => 239550
[patent_doc_number] => 07592267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-22
[patent_title] => 'Method for manufacturing semiconductor silicon substrate and apparatus for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/600105
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[pdf_file] => patents/07/592/07592267.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/600105 | Method for manufacturing semiconductor silicon substrate and apparatus for manufacturing the same | Nov 15, 2006 | Issued |
Array
(
[id] => 7691970
[patent_doc_number] => 20070232063
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'METHOD FOR REDUCING POLISH-INDUCED DAMAGE IN A CONTACT STRUCTURE BY FORMING A CAPPING LAYER'
[patent_app_type] => utility
[patent_app_number] => 11/559652
[patent_app_country] => US
[patent_app_date] => 2006-11-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/559652 | Method for reducing polish-induced damage in a contact structure by forming a capping layer | Nov 13, 2006 | Issued |
Array
(
[id] => 363451
[patent_doc_number] => 07482262
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[patent_title] => 'Method of manufacturing semiconductor device'
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Array
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[id] => 4557495
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Array
(
[id] => 337981
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/558972 | Growth of a semiconductor layer structure | Nov 12, 2006 | Issued |
Array
(
[id] => 4901754
[patent_doc_number] => 20080111166
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Array
(
[id] => 369827
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Array
(
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Array
(
[id] => 4669932
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[patent_title] => 'Method for fabricating a recess gate in a semiconductor device'
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Array
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[patent_title] => 'INTEGRATED CIRCUIT INTERCONNECT LINES HAVING REDUCED LINE RESISTANCE'
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/556802 | Interconnect layers without electromigration | Nov 5, 2006 | Issued |