Search

Mikado Ryan Buiz

Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )

Most Active Art Unit
3506
Art Unit(s)
3731, 2899, 3506
Total Applications
2305
Issued Applications
2195
Pending Applications
18
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4692820 [patent_doc_number] => 20080085591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Novel Gate Structure with Low Resistance for High Power Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 11/539482 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6137 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085591.pdf [firstpage_image] =>[orig_patent_app_number] => 11539482 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/539482
Gate structure with low resistance for high power semiconductor devices Oct 5, 2006 Issued
Array ( [id] => 576399 [patent_doc_number] => 07456067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Method with high gapfill capability for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/539612 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 4451 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456067.pdf [firstpage_image] =>[orig_patent_app_number] => 11539612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/539612
Method with high gapfill capability for semiconductor devices Oct 5, 2006 Issued
Array ( [id] => 5194004 [patent_doc_number] => 20070082488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/543791 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4956 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20070082488.pdf [firstpage_image] =>[orig_patent_app_number] => 11543791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543791
Semiconductor device and manufacturing method thereof Oct 5, 2006 Issued
Array ( [id] => 565322 [patent_doc_number] => 07465643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Semiconductor device with fixed channel ions' [patent_app_type] => utility [patent_app_number] => 11/543071 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 1977 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/465/07465643.pdf [firstpage_image] =>[orig_patent_app_number] => 11543071 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/543071
Semiconductor device with fixed channel ions Oct 4, 2006 Issued
Array ( [id] => 373327 [patent_doc_number] => 07473630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/542212 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7841 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/473/07473630.pdf [firstpage_image] =>[orig_patent_app_number] => 11542212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/542212
Semiconductor device and method for manufacturing same Oct 3, 2006 Issued
Array ( [id] => 5205084 [patent_doc_number] => 20070026566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Phase change memory with damascene memory element' [patent_app_type] => utility [patent_app_number] => 11/542712 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3961 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026566.pdf [firstpage_image] =>[orig_patent_app_number] => 11542712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/542712
Phase change memory with damascene memory element Oct 3, 2006 Issued
Array ( [id] => 5136055 [patent_doc_number] => 20070077684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Resistance welded solder crimp for joining stranded wire to a copper lead-frame' [patent_app_type] => utility [patent_app_number] => 11/541602 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20070077684.pdf [firstpage_image] =>[orig_patent_app_number] => 11541602 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/541602
Resistance welded solder crimp for joining stranded wire to a copper lead-frame Oct 2, 2006 Issued
Array ( [id] => 5177625 [patent_doc_number] => 20070178685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'METHOD OF INCREASING THE ETCH SELECTIVITY IN A CONTACT STRUCTURE OF SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 11/538111 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5364 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20070178685.pdf [firstpage_image] =>[orig_patent_app_number] => 11538111 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538111
Method of increasing the etch selectivity in a contact structure of semiconductor devices Oct 2, 2006 Issued
Array ( [id] => 573911 [patent_doc_number] => 07459396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Method for thin film deposition using multi-tray film precursor evaporation system' [patent_app_type] => utility [patent_app_number] => 11/537575 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7617 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459396.pdf [firstpage_image] =>[orig_patent_app_number] => 11537575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/537575
Method for thin film deposition using multi-tray film precursor evaporation system Sep 28, 2006 Issued
Array ( [id] => 585201 [patent_doc_number] => 07442627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Transparent conductive layer forming method, transparent conductive layer formed by the method, and material comprising the layer' [patent_app_type] => utility [patent_app_number] => 11/536910 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 14870 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442627.pdf [firstpage_image] =>[orig_patent_app_number] => 11536910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/536910
Transparent conductive layer forming method, transparent conductive layer formed by the method, and material comprising the layer Sep 28, 2006 Issued
Array ( [id] => 322550 [patent_doc_number] => 07517782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Method of forming a metal layer over a patterned dielectric by wet chemical deposition including an electroless and a powered phase' [patent_app_type] => utility [patent_app_number] => 11/536041 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 7410 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/517/07517782.pdf [firstpage_image] =>[orig_patent_app_number] => 11536041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/536041
Method of forming a metal layer over a patterned dielectric by wet chemical deposition including an electroless and a powered phase Sep 27, 2006 Issued
Array ( [id] => 373331 [patent_doc_number] => 07473634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Method for integrated substrate processing in copper metallization' [patent_app_type] => utility [patent_app_number] => 11/536161 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 11761 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/473/07473634.pdf [firstpage_image] =>[orig_patent_app_number] => 11536161 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/536161
Method for integrated substrate processing in copper metallization Sep 27, 2006 Issued
Array ( [id] => 373695 [patent_doc_number] => 07473999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Semiconductor chip and process for forming the same' [patent_app_type] => utility [patent_app_number] => 11/534672 [patent_app_country] => US [patent_app_date] => 2006-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 61 [patent_no_of_words] => 23971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/473/07473999.pdf [firstpage_image] =>[orig_patent_app_number] => 11534672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/534672
Semiconductor chip and process for forming the same Sep 23, 2006 Issued
Array ( [id] => 5063115 [patent_doc_number] => 20070224755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Semiconductor device manufacturing method including oblique ion implantation process and reticle pattern forming method' [patent_app_type] => utility [patent_app_number] => 11/524945 [patent_app_country] => US [patent_app_date] => 2006-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8423 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20070224755.pdf [firstpage_image] =>[orig_patent_app_number] => 11524945 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524945
Semiconductor device manufacturing method including oblique ion implantation process and reticle pattern forming method Sep 21, 2006 Issued
Array ( [id] => 5107108 [patent_doc_number] => 20070065986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Method for manufacturing substrate with cavity' [patent_app_type] => utility [patent_app_number] => 11/524402 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3325 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20070065986.pdf [firstpage_image] =>[orig_patent_app_number] => 11524402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524402
Method for manufacturing substrate with cavity Sep 20, 2006 Issued
Array ( [id] => 363389 [patent_doc_number] => 07482199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Self alignment features for an electronic assembly' [patent_app_type] => utility [patent_app_number] => 11/533532 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482199.pdf [firstpage_image] =>[orig_patent_app_number] => 11533532 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/533532
Self alignment features for an electronic assembly Sep 19, 2006 Issued
Array ( [id] => 7523424 [patent_doc_number] => 08026583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Flip-chip module and method for the production thereof' [patent_app_type] => utility [patent_app_number] => 12/065830 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 6387 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/026/08026583.pdf [firstpage_image] =>[orig_patent_app_number] => 12065830 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/065830
Flip-chip module and method for the production thereof Sep 12, 2006 Issued
Array ( [id] => 356251 [patent_doc_number] => 07488687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers' [patent_app_type] => utility [patent_app_number] => 11/530952 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/488/07488687.pdf [firstpage_image] =>[orig_patent_app_number] => 11530952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/530952
Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers Sep 11, 2006 Issued
Array ( [id] => 4701881 [patent_doc_number] => 20080061403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Dielectric layers for metal lines in semiconductor chips' [patent_app_type] => utility [patent_app_number] => 11/530116 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061403.pdf [firstpage_image] =>[orig_patent_app_number] => 11530116 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/530116
Dielectric layers for metal lines in semiconductor chips Sep 7, 2006 Issued
Array ( [id] => 5095676 [patent_doc_number] => 20070117285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor' [patent_app_type] => utility [patent_app_number] => 11/469651 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2639 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117285.pdf [firstpage_image] =>[orig_patent_app_number] => 11469651 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469651
Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor Aug 31, 2006 Issued
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