Search

Mikado Ryan Buiz

Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )

Most Active Art Unit
3506
Art Unit(s)
3731, 2899, 3506
Total Applications
2305
Issued Applications
2195
Pending Applications
18
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 557425 [patent_doc_number] => 07470581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Electromagnetic waveguide' [patent_app_type] => utility [patent_app_number] => 11/494429 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/470/07470581.pdf [firstpage_image] =>[orig_patent_app_number] => 11494429 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/494429
Electromagnetic waveguide Jul 26, 2006 Issued
Array ( [id] => 4657718 [patent_doc_number] => 20080026579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'COPPER DAMASCENE PROCESS' [patent_app_type] => utility [patent_app_number] => 11/459931 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2710 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20080026579.pdf [firstpage_image] =>[orig_patent_app_number] => 11459931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459931
COPPER DAMASCENE PROCESS Jul 24, 2006 Abandoned
Array ( [id] => 289008 [patent_doc_number] => 07547621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'LPCVD gate hard mask' [patent_app_type] => utility [patent_app_number] => 11/492316 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2390 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/547/07547621.pdf [firstpage_image] =>[orig_patent_app_number] => 11492316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492316
LPCVD gate hard mask Jul 24, 2006 Issued
Array ( [id] => 267127 [patent_doc_number] => 07566652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Electrically inactive via for electromigration reliability improvement' [patent_app_type] => utility [patent_app_number] => 11/491846 [patent_app_country] => US [patent_app_date] => 2006-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7525 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/566/07566652.pdf [firstpage_image] =>[orig_patent_app_number] => 11491846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/491846
Electrically inactive via for electromigration reliability improvement Jul 23, 2006 Issued
Array ( [id] => 236269 [patent_doc_number] => 07595250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/490252 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 77 [patent_no_of_words] => 12986 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595250.pdf [firstpage_image] =>[orig_patent_app_number] => 11490252 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490252
Semiconductor device and method of manufacturing the same Jul 20, 2006 Issued
Array ( [id] => 142708 [patent_doc_number] => 07687910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/485636 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4721 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/687/07687910.pdf [firstpage_image] =>[orig_patent_app_number] => 11485636 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485636
Semiconductor device and method of fabricating the same Jul 12, 2006 Issued
Array ( [id] => 132666 [patent_doc_number] => 07696086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Fabricating method of an interconnect structure' [patent_app_type] => utility [patent_app_number] => 11/309201 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3272 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696086.pdf [firstpage_image] =>[orig_patent_app_number] => 11309201 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/309201
Fabricating method of an interconnect structure Jul 12, 2006 Issued
Array ( [id] => 303550 [patent_doc_number] => 07534687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/486555 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4283 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/534/07534687.pdf [firstpage_image] =>[orig_patent_app_number] => 11486555 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486555
Semiconductor device and method for manufacturing the same Jul 12, 2006 Issued
Array ( [id] => 5072988 [patent_doc_number] => 20070012963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'CMOS image sensor and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/486456 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20070012963.pdf [firstpage_image] =>[orig_patent_app_number] => 11486456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486456
CMOS image sensor and manufacturing method thereof Jul 12, 2006 Issued
Array ( [id] => 4803171 [patent_doc_number] => 20080014759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Method for fabricating a gate dielectric layer utilized in a gate structure' [patent_app_type] => utility [patent_app_number] => 11/485546 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4184 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014759.pdf [firstpage_image] =>[orig_patent_app_number] => 11485546 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485546
Method for fabricating a gate dielectric layer utilized in a gate structure Jul 11, 2006 Abandoned
Array ( [id] => 53880 [patent_doc_number] => 07767570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Dummy vias for damascene process' [patent_app_type] => utility [patent_app_number] => 11/457032 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 5251 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/767/07767570.pdf [firstpage_image] =>[orig_patent_app_number] => 11457032 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457032
Dummy vias for damascene process Jul 11, 2006 Issued
Array ( [id] => 4432545 [patent_doc_number] => 07897417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Hybrid nanocomposite semiconductor material, and method of producing inorganic semiconductor therefor' [patent_app_type] => utility [patent_app_number] => 11/988646 [patent_app_country] => US [patent_app_date] => 2006-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6133 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/897/07897417.pdf [firstpage_image] =>[orig_patent_app_number] => 11988646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/988646
Hybrid nanocomposite semiconductor material, and method of producing inorganic semiconductor therefor Jul 10, 2006 Issued
Array ( [id] => 4733890 [patent_doc_number] => 20080050869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'DUAL STRESS LINER DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 11/428692 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20080050869.pdf [firstpage_image] =>[orig_patent_app_number] => 11428692 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428692
Dual stress liner device and method Jul 4, 2006 Issued
Array ( [id] => 583819 [patent_doc_number] => 07446034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Process for making a metal seed layer' [patent_app_type] => utility [patent_app_number] => 11/426822 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4465 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446034.pdf [firstpage_image] =>[orig_patent_app_number] => 11426822 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426822
Process for making a metal seed layer Jun 26, 2006 Issued
Array ( [id] => 5196740 [patent_doc_number] => 20070296058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Semiconductor structure of a high side driver and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/474375 [patent_app_country] => US [patent_app_date] => 2006-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2488 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20070296058.pdf [firstpage_image] =>[orig_patent_app_number] => 11474375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/474375
Semiconductor structure of a high side driver and method for manufacturing the same Jun 25, 2006 Issued
Array ( [id] => 299772 [patent_doc_number] => 07537971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Method for fabricating CMOS image sensor' [patent_app_type] => utility [patent_app_number] => 11/474409 [patent_app_country] => US [patent_app_date] => 2006-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2774 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/537/07537971.pdf [firstpage_image] =>[orig_patent_app_number] => 11474409 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/474409
Method for fabricating CMOS image sensor Jun 25, 2006 Issued
Array ( [id] => 582992 [patent_doc_number] => 07445958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Semiconductor device having a leading wiring layer' [patent_app_type] => utility [patent_app_number] => 11/474469 [patent_app_country] => US [patent_app_date] => 2006-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 28 [patent_no_of_words] => 9386 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/445/07445958.pdf [firstpage_image] =>[orig_patent_app_number] => 11474469 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/474469
Semiconductor device having a leading wiring layer Jun 25, 2006 Issued
Array ( [id] => 185246 [patent_doc_number] => 07645696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-12 [patent_title] => 'Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer' [patent_app_type] => utility [patent_app_number] => 11/473618 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5796 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/645/07645696.pdf [firstpage_image] =>[orig_patent_app_number] => 11473618 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/473618
Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer Jun 21, 2006 Issued
Array ( [id] => 281754 [patent_doc_number] => 07553754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Electronic device, method of manufacture of the same, and sputtering target' [patent_app_type] => utility [patent_app_number] => 11/471595 [patent_app_country] => US [patent_app_date] => 2006-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 43 [patent_no_of_words] => 16314 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/553/07553754.pdf [firstpage_image] =>[orig_patent_app_number] => 11471595 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/471595
Electronic device, method of manufacture of the same, and sputtering target Jun 20, 2006 Issued
Array ( [id] => 589290 [patent_doc_number] => 07435654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/452828 [patent_app_country] => US [patent_app_date] => 2006-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 8288 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/435/07435654.pdf [firstpage_image] =>[orig_patent_app_number] => 11452828 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/452828
Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same Jun 13, 2006 Issued
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