Mikado Ryan Buiz

Array ( [id] => 1172340 [patent_doc_number] => 06750069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Minimally spaced MRAM structures' [patent_app_type] => B2 [patent_app_number] => 10/454479 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4067 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750069.pdf [firstpage_image] =>[orig_patent_app_number] => 10454479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1046747 [patent_doc_number] => 06864141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-08 [patent_title] => 'Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion beams' [patent_app_type] => utility [patent_app_number] => 10/453118 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 6638 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864141.pdf [firstpage_image] =>[orig_patent_app_number] => 10453118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1040514 [patent_doc_number] => 06869812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'High power AllnGaN based multi-chip light emitting diode' [patent_app_type] => utility [patent_app_number] => 10/438108 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6503 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869812.pdf [firstpage_image] =>[orig_patent_app_number] => 10438108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1232369 [patent_doc_number] => 06693317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Optical sensor by using tunneling diode' [patent_app_type] => B2 [patent_app_number] => 10/437147 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2279 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693317.pdf [firstpage_image] =>[orig_patent_app_number] => 10437147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1245752 [patent_doc_number] => 06677238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'System and methods for fabrication of a thin film pattern' [patent_app_type] => B2 [patent_app_number] => 10/425622 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5819 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677238.pdf [firstpage_image] =>[orig_patent_app_number] => 10425622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7269945 [patent_doc_number] => 20040058463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Method of forming a p-type group II-VI semiconductor crystal layer on a substrate' [patent_app_type] => new [patent_app_number] => 10/422568 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7250 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20040058463.pdf [firstpage_image] =>[orig_patent_app_number] => 10422568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1167661 [patent_doc_number] => 06759699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Storage element and SRAM cell structures using vertical FETS controlled by adjacent junction bias through shallow trench isolation' [patent_app_type] => B1 [patent_app_number] => 10/420263 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 6177 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759699.pdf [firstpage_image] =>[orig_patent_app_number] => 10420263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1134049 [patent_doc_number] => 06784030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Laser illumination system' [patent_app_type] => B2 [patent_app_number] => 10/406309 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5802 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784030.pdf [firstpage_image] =>[orig_patent_app_number] => 10406309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1228137 [patent_doc_number] => 06696306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Methods of fabricating layered structure and semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/400378 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7977 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696306.pdf [firstpage_image] =>[orig_patent_app_number] => 10400378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1210955 [patent_doc_number] => 06713858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Flip-chip package with optimized encapsulant adhesion and method' [patent_app_type] => B2 [patent_app_number] => 10/404774 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3526 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713858.pdf [firstpage_image] =>[orig_patent_app_number] => 10404774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6846000 [patent_doc_number] => 20030165167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Semiconductor laser device and wire bonding method capable of easily performing reliable wire bonding' [patent_app_type] => new [patent_app_number] => 10/396402 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8622 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20030165167.pdf [firstpage_image] =>[orig_patent_app_number] => 10396402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6821790 [patent_doc_number] => 20030219951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Semiconductor constructions, and methods of forming semiconductor constructions' [patent_app_type] => new [patent_app_number] => 10/388721 [patent_app_country] => US [patent_app_date] => 2003-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6322 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20030219951.pdf [firstpage_image] =>[orig_patent_app_number] => 10388721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6706432 [patent_doc_number] => 20030153166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Transistor and method of making the same' [patent_app_type] => new [patent_app_number] => 10/374181 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4382 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20030153166.pdf [firstpage_image] =>[orig_patent_app_number] => 10374181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6706453 [patent_doc_number] => 20030153187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Process for manufacturing semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/369716 [patent_app_country] => US [patent_app_date] => 2003-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9781 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20030153187.pdf [firstpage_image] =>[orig_patent_app_number] => 10369716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6740429 [patent_doc_number] => 20030157798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Method for fabricating a component, and component having a metal layer and an insulation layer' [patent_app_type] => new [patent_app_number] => 10/370858 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7838 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20030157798.pdf [firstpage_image] =>[orig_patent_app_number] => 10370858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6740419 [patent_doc_number] => 20030157788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Method of suppressing void formation in a metal line' [patent_app_type] => new [patent_app_number] => 10/366070 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20030157788.pdf [firstpage_image] =>[orig_patent_app_number] => 10366070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8446807 [patent_doc_number] => 08288862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Multiple die stack package' [patent_app_type] => utility [patent_app_number] => 10/361814 [patent_app_country] => US [patent_app_date] => 2003-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3399 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10361814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1220585 [patent_doc_number] => 06703317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method to neutralize charge imbalance following a wafer cleaning process' [patent_app_type] => B1 [patent_app_number] => 10/356248 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703317.pdf [firstpage_image] =>[orig_patent_app_number] => 10356248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1089141 [patent_doc_number] => 06828208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-07 [patent_title] => 'Method of fabricating shallow trench isolation structure' [patent_app_type] => B2 [patent_app_number] => 10/248538 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2246 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/828/06828208.pdf [firstpage_image] =>[orig_patent_app_number] => 10248538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1248242 [patent_doc_number] => 06673696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Post trench fill oxidation process for strained silicon processes' [patent_app_type] => B1 [patent_app_number] => 10/341848 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673696.pdf [firstpage_image] =>[orig_patent_app_number] => 10341848 [rel_patent_id] =>[rel_patent_doc_number] =>)