Search

Mikado Ryan Buiz

Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )

Most Active Art Unit
3506
Art Unit(s)
3731, 2899, 3506
Total Applications
2305
Issued Applications
2195
Pending Applications
18
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6683460 [patent_doc_number] => 20030119324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method for manufacturing metal line contact plug of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/329938 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119324.pdf [firstpage_image] =>[orig_patent_app_number] => 10329938 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329938
Method for manufacturing metal line contact plug of semiconductor device Dec 25, 2002 Issued
Array ( [id] => 7471473 [patent_doc_number] => 20040121544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'HIGH-K TUNNELING DIELECTRIC FOR READ ONLY MEMORY DEVICE AND FABRICATION METHOD THEREOF' [patent_app_type] => new [patent_app_number] => 10/248179 [patent_app_country] => US [patent_app_date] => 2002-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3052 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121544.pdf [firstpage_image] =>[orig_patent_app_number] => 10248179 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/248179
High-K tunneling dielectric for read only memory device and fabrication method thereof Dec 23, 2002 Issued
Array ( [id] => 1239727 [patent_doc_number] => 06686285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing' [patent_app_type] => B2 [patent_app_number] => 10/326378 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 4430 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686285.pdf [firstpage_image] =>[orig_patent_app_number] => 10326378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/326378
Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing Dec 22, 2002 Issued
Array ( [id] => 1156193 [patent_doc_number] => 06762104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Method for fabricating semiconductor device with improved refresh characteristics' [patent_app_type] => B2 [patent_app_number] => 10/328098 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2084 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762104.pdf [firstpage_image] =>[orig_patent_app_number] => 10328098 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328098
Method for fabricating semiconductor device with improved refresh characteristics Dec 22, 2002 Issued
Array ( [id] => 1152258 [patent_doc_number] => 06767822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Method of forming metallic film and method of producing semiconductor system' [patent_app_type] => B2 [patent_app_number] => 10/312478 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5466 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/767/06767822.pdf [firstpage_image] =>[orig_patent_app_number] => 10312478 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/312478
Method of forming metallic film and method of producing semiconductor system Dec 22, 2002 Issued
Array ( [id] => 7471633 [patent_doc_number] => 20040121577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'METHOD FOR PROVIDING A DUMMY FEATURE AND STRUCTURE THEREOF' [patent_app_type] => new [patent_app_number] => 10/327498 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9112 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121577.pdf [firstpage_image] =>[orig_patent_app_number] => 10327498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327498
Method for providing a dummy feature and structure thereof Dec 19, 2002 Issued
Array ( [id] => 6683459 [patent_doc_number] => 20030119323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method for fabricating transistor in semiconductor device' [patent_app_type] => new [patent_app_number] => 10/325318 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1480 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119323.pdf [firstpage_image] =>[orig_patent_app_number] => 10325318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/325318
Method for fabricating transistor in semiconductor device Dec 18, 2002 Abandoned
Array ( [id] => 1156199 [patent_doc_number] => 06762105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Short channel transistor fabrication method for semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/323328 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1513 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762105.pdf [firstpage_image] =>[orig_patent_app_number] => 10323328 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/323328
Short channel transistor fabrication method for semiconductor device Dec 17, 2002 Issued
Array ( [id] => 1080486 [patent_doc_number] => 06835644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'Method for making interconnect structures' [patent_app_type] => B2 [patent_app_number] => 10/319348 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2894 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835644.pdf [firstpage_image] =>[orig_patent_app_number] => 10319348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/319348
Method for making interconnect structures Dec 15, 2002 Issued
Array ( [id] => 6761496 [patent_doc_number] => 20030124858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Fabrication method for semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/319580 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9132 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124858.pdf [firstpage_image] =>[orig_patent_app_number] => 10319580 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/319580
Fabrication method for semiconductor integrated circuit device Dec 15, 2002 Abandoned
Array ( [id] => 6649814 [patent_doc_number] => 20030104706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Wet-etching method and method for manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/309038 [patent_app_country] => US [patent_app_date] => 2002-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9006 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20030104706.pdf [firstpage_image] =>[orig_patent_app_number] => 10309038 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/309038
Wet-etching method and method for manufacturing semiconductor device Dec 3, 2002 Issued
Array ( [id] => 7466628 [patent_doc_number] => 20040101978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Method of forming a barrier layer of a tunneling magnetoresistive sensor' [patent_app_type] => new [patent_app_number] => 10/304841 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5674 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20040101978.pdf [firstpage_image] =>[orig_patent_app_number] => 10304841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/304841
Method of forming a barrier layer of a tunneling magnetoresistive sensor Nov 24, 2002 Issued
Array ( [id] => 1223705 [patent_doc_number] => 06699754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Flash memory cell and method for fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/302285 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1766 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/699/06699754.pdf [firstpage_image] =>[orig_patent_app_number] => 10302285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302285
Flash memory cell and method for fabricating the same Nov 21, 2002 Issued
Array ( [id] => 1241166 [patent_doc_number] => 06682989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Plating a conductive material on a dielectric material' [patent_app_type] => B1 [patent_app_number] => 10/300378 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1789 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/682/06682989.pdf [firstpage_image] =>[orig_patent_app_number] => 10300378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300378
Plating a conductive material on a dielectric material Nov 19, 2002 Issued
Array ( [id] => 662623 [patent_doc_number] => 07101739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Method for forming a schottky diode on a silicon carbide substrate' [patent_app_type] => utility [patent_app_number] => 10/300208 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2566 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/101/07101739.pdf [firstpage_image] =>[orig_patent_app_number] => 10300208 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300208
Method for forming a schottky diode on a silicon carbide substrate Nov 19, 2002 Issued
Array ( [id] => 1239691 [patent_doc_number] => 06686267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode' [patent_app_type] => B1 [patent_app_number] => 10/298915 [patent_app_country] => US [patent_app_date] => 2002-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11548 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686267.pdf [firstpage_image] =>[orig_patent_app_number] => 10298915 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/298915
Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode Nov 17, 2002 Issued
Array ( [id] => 1231396 [patent_doc_number] => 06693027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Method for configuring a device to include a negative differential resistance (NDR) characteristic' [patent_app_type] => B1 [patent_app_number] => 10/298917 [patent_app_country] => US [patent_app_date] => 2002-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693027.pdf [firstpage_image] =>[orig_patent_app_number] => 10298917 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/298917
Method for configuring a device to include a negative differential resistance (NDR) characteristic Nov 17, 2002 Issued
Array ( [id] => 6801307 [patent_doc_number] => 20030096472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Methods for forming capacitors on semiconductor substrates' [patent_app_type] => new [patent_app_number] => 10/295348 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10887 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096472.pdf [firstpage_image] =>[orig_patent_app_number] => 10295348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/295348
Methods for forming capacitors on semiconductor substrates Nov 14, 2002 Issued
Array ( [id] => 6730316 [patent_doc_number] => 20030186506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Split gate flash memory and formation method thereof' [patent_app_type] => new [patent_app_number] => 10/295298 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2069 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20030186506.pdf [firstpage_image] =>[orig_patent_app_number] => 10295298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/295298
Split gate flash memory and formation method thereof Nov 14, 2002 Issued
Array ( [id] => 7365084 [patent_doc_number] => 20040092054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Grounded gate for reducing dark current in CMOS image sensors' [patent_app_type] => new [patent_app_number] => 10/291728 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5314 [patent_no_of_claims] => 126 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092054.pdf [firstpage_image] =>[orig_patent_app_number] => 10291728 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291728
Gated isolation structure for imagers Nov 11, 2002 Issued
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