Search

Mikado Ryan Buiz

Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )

Most Active Art Unit
3506
Art Unit(s)
3731, 2899, 3506
Total Applications
2305
Issued Applications
2195
Pending Applications
18
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7964397 [patent_doc_number] => 06680228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Capacitor in semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/268964 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1579 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680228.pdf [firstpage_image] =>[orig_patent_app_number] => 10268964 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268964
Capacitor in semiconductor device Oct 10, 2002 Issued
Array ( [id] => 1273812 [patent_doc_number] => 06649469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Methods of forming capacitors' [patent_app_type] => B1 [patent_app_number] => 10/269302 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 2831 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649469.pdf [firstpage_image] =>[orig_patent_app_number] => 10269302 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269302
Methods of forming capacitors Oct 10, 2002 Issued
Array ( [id] => 7615031 [patent_doc_number] => 06897495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Field effect transistor and manufacturing method therefor' [patent_app_type] => utility [patent_app_number] => 10/270708 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 40 [patent_no_of_words] => 9852 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897495.pdf [firstpage_image] =>[orig_patent_app_number] => 10270708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/270708
Field effect transistor and manufacturing method therefor Oct 10, 2002 Issued
Array ( [id] => 1073672 [patent_doc_number] => 06838337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Sense amplifier and architecture for open digit arrays' [patent_app_type] => utility [patent_app_number] => 10/267991 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2862 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838337.pdf [firstpage_image] =>[orig_patent_app_number] => 10267991 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/267991
Sense amplifier and architecture for open digit arrays Oct 9, 2002 Issued
Array ( [id] => 1290947 [patent_doc_number] => 06630365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-07 [patent_title] => 'Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures' [patent_app_type] => B2 [patent_app_number] => 10/266464 [patent_app_country] => US [patent_app_date] => 2002-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 11096 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630365.pdf [firstpage_image] =>[orig_patent_app_number] => 10266464 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/266464
Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures Oct 7, 2002 Issued
Array ( [id] => 1106085 [patent_doc_number] => 06812493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Thin-film semiconductor element and method of producing same' [patent_app_type] => B2 [patent_app_number] => 10/240648 [patent_app_country] => US [patent_app_date] => 2002-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 57 [patent_no_of_words] => 12662 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812493.pdf [firstpage_image] =>[orig_patent_app_number] => 10240648 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/240648
Thin-film semiconductor element and method of producing same Oct 3, 2002 Issued
Array ( [id] => 1211746 [patent_doc_number] => RE038466 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device' [patent_app_type] => E1 [patent_app_number] => 10/263070 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 42 [patent_no_of_words] => 12610 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038466.pdf [firstpage_image] =>[orig_patent_app_number] => 10263070 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263070
Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device Oct 2, 2002 Issued
Array ( [id] => 7450535 [patent_doc_number] => 20040067660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate' [patent_app_type] => new [patent_app_number] => 10/263638 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20040067660.pdf [firstpage_image] =>[orig_patent_app_number] => 10263638 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263638
Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate Oct 2, 2002 Issued
Array ( [id] => 1354621 [patent_doc_number] => 06576530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Method of fabricating shallow trench isolation' [patent_app_type] => B1 [patent_app_number] => 10/261648 [patent_app_country] => US [patent_app_date] => 2002-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1745 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576530.pdf [firstpage_image] =>[orig_patent_app_number] => 10261648 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261648
Method of fabricating shallow trench isolation Sep 30, 2002 Issued
Array ( [id] => 1012641 [patent_doc_number] => 06897112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Method for fabricating an integrated semiconductor configuration with the aid of thermal oxidation, related semiconductor configuration, and related memory unit' [patent_app_type] => utility [patent_app_number] => 10/262148 [patent_app_country] => US [patent_app_date] => 2002-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2646 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897112.pdf [firstpage_image] =>[orig_patent_app_number] => 10262148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/262148
Method for fabricating an integrated semiconductor configuration with the aid of thermal oxidation, related semiconductor configuration, and related memory unit Sep 30, 2002 Issued
Array ( [id] => 7280923 [patent_doc_number] => 20040063300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control' [patent_app_type] => new [patent_app_number] => 10/262168 [patent_app_country] => US [patent_app_date] => 2002-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4573 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063300.pdf [firstpage_image] =>[orig_patent_app_number] => 10262168 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/262168
Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control Sep 30, 2002 Issued
Array ( [id] => 1172369 [patent_doc_number] => 06750073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Method for forming a mask pattern' [patent_app_type] => B2 [patent_app_number] => 10/261708 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2565 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750073.pdf [firstpage_image] =>[orig_patent_app_number] => 10261708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261708
Method for forming a mask pattern Sep 29, 2002 Issued
Array ( [id] => 6742962 [patent_doc_number] => 20030020145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Semiconductor device having reinforced coupling between solder balls and substrate' [patent_app_type] => new [patent_app_number] => 10/256364 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20030020145.pdf [firstpage_image] =>[orig_patent_app_number] => 10256364 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256364
Semiconductor device having reinforced coupling between solder balls and substrate Sep 26, 2002 Issued
Array ( [id] => 1220524 [patent_doc_number] => 06703285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method for manufacturing capacitor structure, and method for manufacturing capacitor element' [patent_app_type] => B2 [patent_app_number] => 10/254788 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 7178 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703285.pdf [firstpage_image] =>[orig_patent_app_number] => 10254788 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254788
Method for manufacturing capacitor structure, and method for manufacturing capacitor element Sep 25, 2002 Issued
Array ( [id] => 6870170 [patent_doc_number] => 20030082859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/252838 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 23815 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20030082859.pdf [firstpage_image] =>[orig_patent_app_number] => 10252838 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252838
Method of manufacturing a semiconductor device Sep 23, 2002 Issued
Array ( [id] => 1291028 [patent_doc_number] => 06630377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process' [patent_app_type] => B1 [patent_app_number] => 10/246228 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 3279 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630377.pdf [firstpage_image] =>[orig_patent_app_number] => 10246228 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246228
Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process Sep 17, 2002 Issued
Array ( [id] => 6745279 [patent_doc_number] => 20030022462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures' [patent_app_type] => new [patent_app_number] => 10/246318 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11205 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022462.pdf [firstpage_image] =>[orig_patent_app_number] => 10246318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246318
Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures Sep 16, 2002 Issued
Array ( [id] => 1085608 [patent_doc_number] => 06830953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Suppression of MOSFET gate leakage current' [patent_app_type] => B1 [patent_app_number] => 10/245428 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3538 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/830/06830953.pdf [firstpage_image] =>[orig_patent_app_number] => 10245428 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/245428
Suppression of MOSFET gate leakage current Sep 16, 2002 Issued
Array ( [id] => 1106305 [patent_doc_number] => 06812569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Semiconductor device using bumps, method for fabricating same, and method for forming bumps' [patent_app_type] => B2 [patent_app_number] => 10/245697 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7405 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812569.pdf [firstpage_image] =>[orig_patent_app_number] => 10245697 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/245697
Semiconductor device using bumps, method for fabricating same, and method for forming bumps Sep 15, 2002 Issued
Array ( [id] => 1146347 [patent_doc_number] => 06773988 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Memory wordline spacer' [patent_app_type] => B1 [patent_app_number] => 10/243108 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3031 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/773/06773988.pdf [firstpage_image] =>[orig_patent_app_number] => 10243108 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/243108
Memory wordline spacer Sep 12, 2002 Issued
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