Mikado Ryan Buiz
Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )
Most Active Art Unit | 3506 |
Art Unit(s) | 3731, 2899, 3506 |
Total Applications | 2305 |
Issued Applications | 2195 |
Pending Applications | 18 |
Abandoned Applications | 92 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1021401
[patent_doc_number] => 06887733
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Method of fabricating electronic devices'
[patent_app_type] => utility
[patent_app_number] => 10/242068
[patent_app_country] => US
[patent_app_date] => 2002-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3098
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/887/06887733.pdf
[firstpage_image] =>[orig_patent_app_number] => 10242068
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/242068 | Method of fabricating electronic devices | Sep 10, 2002 | Issued |
Array
(
[id] => 1123436
[patent_doc_number] => 06794281
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-21
[patent_title] => 'Dual metal gate transistors for CMOS process'
[patent_app_type] => B2
[patent_app_number] => 10/238314
[patent_app_country] => US
[patent_app_date] => 2002-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3048
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/794/06794281.pdf
[firstpage_image] =>[orig_patent_app_number] => 10238314
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/238314 | Dual metal gate transistors for CMOS process | Sep 9, 2002 | Issued |
Array
(
[id] => 7352942
[patent_doc_number] => 20040048453
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-11
[patent_title] => 'Method for polysilicon crystallization by simultaneous laser and rapid thermal annealing'
[patent_app_type] => new
[patent_app_number] => 10/236608
[patent_app_country] => US
[patent_app_date] => 2002-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2850
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20040048453.pdf
[firstpage_image] =>[orig_patent_app_number] => 10236608
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/236608 | Method for polysilicon crystallization by simultaneous laser and rapid thermal annealing | Sep 5, 2002 | Issued |
Array
(
[id] => 1274036
[patent_doc_number] => 06649514
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-18
[patent_title] => 'EEPROM device having improved data retention and process for fabricating the device'
[patent_app_type] => B1
[patent_app_number] => 10/236718
[patent_app_country] => US
[patent_app_date] => 2002-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2835
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/649/06649514.pdf
[firstpage_image] =>[orig_patent_app_number] => 10236718
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/236718 | EEPROM device having improved data retention and process for fabricating the device | Sep 5, 2002 | Issued |
Array
(
[id] => 1150137
[patent_doc_number] => 06774457
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-10
[patent_title] => 'Rectangular contact used as a low voltage fuse element'
[patent_app_type] => B2
[patent_app_number] => 10/235268
[patent_app_country] => US
[patent_app_date] => 2002-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2101
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/774/06774457.pdf
[firstpage_image] =>[orig_patent_app_number] => 10235268
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/235268 | Rectangular contact used as a low voltage fuse element | Sep 4, 2002 | Issued |
Array
(
[id] => 1136336
[patent_doc_number] => 06784483
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-31
[patent_title] => 'Method for preventing hole and electron movement in NROM devices'
[patent_app_type] => B2
[patent_app_number] => 10/236023
[patent_app_country] => US
[patent_app_date] => 2002-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 4698
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/784/06784483.pdf
[firstpage_image] =>[orig_patent_app_number] => 10236023
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/236023 | Method for preventing hole and electron movement in NROM devices | Sep 3, 2002 | Issued |
Array
(
[id] => 1095863
[patent_doc_number] => 06821817
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-23
[patent_title] => 'Premolded cavity IC package'
[patent_app_type] => B1
[patent_app_number] => 10/232678
[patent_app_country] => US
[patent_app_date] => 2002-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 2112
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/821/06821817.pdf
[firstpage_image] =>[orig_patent_app_number] => 10232678
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232678 | Premolded cavity IC package | Sep 2, 2002 | Issued |
Array
(
[id] => 7964363
[patent_doc_number] => 06680245
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-20
[patent_title] => 'Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process'
[patent_app_type] => B1
[patent_app_number] => 10/232129
[patent_app_country] => US
[patent_app_date] => 2002-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 8932
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/680/06680245.pdf
[firstpage_image] =>[orig_patent_app_number] => 10232129
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232129 | Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process | Aug 29, 2002 | Issued |
Array
(
[id] => 7135192
[patent_doc_number] => 20040043591
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'DESIGN LAYOUT METHOD FOR METAL LINES OF AN INTEGRATED CIRCUIT'
[patent_app_type] => new
[patent_app_number] => 10/231938
[patent_app_country] => US
[patent_app_date] => 2002-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3421
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20040043591.pdf
[firstpage_image] =>[orig_patent_app_number] => 10231938
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/231938 | Design layout method for metal lines of an integrated circuit | Aug 29, 2002 | Issued |
Array
(
[id] => 7964385
[patent_doc_number] => 06680234
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-20
[patent_title] => 'Semiconductor device having the effect that the drop in the current gain is kept to the minimum, when the substrate density is amplified and that the variation in the collector current is improved'
[patent_app_type] => B2
[patent_app_number] => 10/230095
[patent_app_country] => US
[patent_app_date] => 2002-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7203
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/680/06680234.pdf
[firstpage_image] =>[orig_patent_app_number] => 10230095
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/230095 | Semiconductor device having the effect that the drop in the current gain is kept to the minimum, when the substrate density is amplified and that the variation in the collector current is improved | Aug 28, 2002 | Issued |
Array
(
[id] => 7131756
[patent_doc_number] => 20040042246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'Method for reducing diffusion through ferromagnetic materials'
[patent_app_type] => new
[patent_app_number] => 10/229139
[patent_app_country] => US
[patent_app_date] => 2002-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2142
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20040042246.pdf
[firstpage_image] =>[orig_patent_app_number] => 10229139
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/229139 | Device having reduced diffusion through ferromagnetic materials | Aug 27, 2002 | Issued |
Array
(
[id] => 1027911
[patent_doc_number] => 06881627
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-19
[patent_title] => 'Flash memory with ultra thin vertical body transistors'
[patent_app_type] => utility
[patent_app_number] => 10/232268
[patent_app_country] => US
[patent_app_date] => 2002-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 30
[patent_no_of_words] => 9101
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/881/06881627.pdf
[firstpage_image] =>[orig_patent_app_number] => 10232268
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232268 | Flash memory with ultra thin vertical body transistors | Aug 27, 2002 | Issued |
Array
(
[id] => 1368124
[patent_doc_number] => 06566280
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-20
[patent_title] => 'Forming polymer features on a substrate'
[patent_app_type] => B1
[patent_app_number] => 10/227678
[patent_app_country] => US
[patent_app_date] => 2002-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2294
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/566/06566280.pdf
[firstpage_image] =>[orig_patent_app_number] => 10227678
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/227678 | Forming polymer features on a substrate | Aug 25, 2002 | Issued |
Array
(
[id] => 1089074
[patent_doc_number] => 06828182
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-07
[patent_title] => 'Epitaxial thin film forming method'
[patent_app_type] => B2
[patent_app_number] => 10/225308
[patent_app_country] => US
[patent_app_date] => 2002-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 5588
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/828/06828182.pdf
[firstpage_image] =>[orig_patent_app_number] => 10225308
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/225308 | Epitaxial thin film forming method | Aug 21, 2002 | Issued |
Array
(
[id] => 1239630
[patent_doc_number] => 06686247
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-03
[patent_title] => 'Self-aligned contacts to gates'
[patent_app_type] => B1
[patent_app_number] => 10/226498
[patent_app_country] => US
[patent_app_date] => 2002-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 5514
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/686/06686247.pdf
[firstpage_image] =>[orig_patent_app_number] => 10226498
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/226498 | Self-aligned contacts to gates | Aug 21, 2002 | Issued |
Array
(
[id] => 6692708
[patent_doc_number] => 20030040140
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-27
[patent_title] => 'Semiconductor memory device and method of manufacturing semiconductor device with chip on chip structure'
[patent_app_type] => new
[patent_app_number] => 10/227083
[patent_app_country] => US
[patent_app_date] => 2002-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3968
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0040/20030040140.pdf
[firstpage_image] =>[orig_patent_app_number] => 10227083
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/227083 | Semiconductor memory device and method of manufacturing semiconductor device with chip on chip structure | Aug 21, 2002 | Issued |
Array
(
[id] => 1397358
[patent_doc_number] => 06531400
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-11
[patent_title] => 'Process for manufacturing semiconductor integrated circuit device'
[patent_app_type] => B2
[patent_app_number] => 10/222848
[patent_app_country] => US
[patent_app_date] => 2002-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 9576
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/531/06531400.pdf
[firstpage_image] =>[orig_patent_app_number] => 10222848
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/222848 | Process for manufacturing semiconductor integrated circuit device | Aug 18, 2002 | Issued |
Array
(
[id] => 1336591
[patent_doc_number] => 06593242
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-15
[patent_title] => 'Process for planarization and recess etching of integrated circuits'
[patent_app_type] => B2
[patent_app_number] => 10/223038
[patent_app_country] => US
[patent_app_date] => 2002-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 2839
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/593/06593242.pdf
[firstpage_image] =>[orig_patent_app_number] => 10223038
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/223038 | Process for planarization and recess etching of integrated circuits | Aug 15, 2002 | Issued |
Array
(
[id] => 6683347
[patent_doc_number] => 20030119211
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'METHOD OF PATTERNING A FERAM CAPACITOR WITH A SIDEWALL DURING BOTTOM ELECTRODE ETCH'
[patent_app_type] => new
[patent_app_number] => 10/222718
[patent_app_country] => US
[patent_app_date] => 2002-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 13593
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20030119211.pdf
[firstpage_image] =>[orig_patent_app_number] => 10222718
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/222718 | Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch | Aug 15, 2002 | Issued |
Array
(
[id] => 1183032
[patent_doc_number] => 06737707
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-18
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => B2
[patent_app_number] => 10/215188
[patent_app_country] => US
[patent_app_date] => 2002-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2852
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/737/06737707.pdf
[firstpage_image] =>[orig_patent_app_number] => 10215188
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/215188 | Semiconductor device and manufacturing method thereof | Aug 8, 2002 | Issued |