Mikado Ryan Buiz
Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )
Most Active Art Unit | 3506 |
Art Unit(s) | 3731, 2899, 3506 |
Total Applications | 2305 |
Issued Applications | 2195 |
Pending Applications | 18 |
Abandoned Applications | 92 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1165504
[patent_doc_number] => 06756298
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-29
[patent_title] => 'Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals'
[patent_app_type] => B2
[patent_app_number] => 10/211855
[patent_app_country] => US
[patent_app_date] => 2002-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3427
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/756/06756298.pdf
[firstpage_image] =>[orig_patent_app_number] => 10211855
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/211855 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals | Jul 31, 2002 | Issued |
Array
(
[id] => 1297544
[patent_doc_number] => 06627538
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-30
[patent_title] => 'Focused ion beam deposition'
[patent_app_type] => B2
[patent_app_number] => 10/209983
[patent_app_country] => US
[patent_app_date] => 2002-07-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/627/06627538.pdf
[firstpage_image] =>[orig_patent_app_number] => 10209983
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/209983 | Focused ion beam deposition | Jul 30, 2002 | Issued |
Array
(
[id] => 7392716
[patent_doc_number] => 20040017726
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Vertical interconnection structure and methods'
[patent_app_type] => new
[patent_app_number] => 10/202105
[patent_app_country] => US
[patent_app_date] => 2002-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0017/20040017726.pdf
[firstpage_image] =>[orig_patent_app_number] => 10202105
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/202105 | Vertical interconnection structure and methods | Jul 22, 2002 | Issued |
Array
(
[id] => 1119834
[patent_doc_number] => 06797613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-28
[patent_title] => 'Process for depositing WSix layers on a high topography with a defined stoichiometry'
[patent_app_type] => B2
[patent_app_number] => 10/196698
[patent_app_country] => US
[patent_app_date] => 2002-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/797/06797613.pdf
[firstpage_image] =>[orig_patent_app_number] => 10196698
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/196698 | Process for depositing WSix layers on a high topography with a defined stoichiometry | Jul 15, 2002 | Issued |
Array
(
[id] => 1046792
[patent_doc_number] => 06864187
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-08
[patent_title] => 'Method of washing a semiconductor wafer'
[patent_app_type] => utility
[patent_app_number] => 10/192728
[patent_app_country] => US
[patent_app_date] => 2002-07-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/864/06864187.pdf
[firstpage_image] =>[orig_patent_app_number] => 10192728
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/192728 | Method of washing a semiconductor wafer | Jul 10, 2002 | Issued |
Array
(
[id] => 6563359
[patent_doc_number] => 20020164865
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-07
[patent_title] => 'Semiconductor device and manufacturing method thereof'
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[pdf_file] => publications/A1/0164/20020164865.pdf
[firstpage_image] =>[orig_patent_app_number] => 10187998
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/187998 | Semiconductor device and manufacturing method thereof | Jul 2, 2002 | Issued |
Array
(
[id] => 7629798
[patent_doc_number] => 06818558
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[patent_kind] => B1
[patent_issue_date] => 2004-11-16
[patent_title] => 'Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices'
[patent_app_type] => B1
[patent_app_number] => 10/185470
[patent_app_country] => US
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[pdf_file] => patents/06/818/06818558.pdf
[firstpage_image] =>[orig_patent_app_number] => 10185470
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/185470 | Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices | Jun 27, 2002 | Issued |
Array
(
[id] => 1188823
[patent_doc_number] => 06734054
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-11
[patent_title] => 'Electrostatic discharge protection circuit device and a manufacturing method for the same'
[patent_app_type] => B2
[patent_app_number] => 10/186011
[patent_app_country] => US
[patent_app_date] => 2002-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2748
[patent_no_of_claims] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/734/06734054.pdf
[firstpage_image] =>[orig_patent_app_number] => 10186011
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/186011 | Electrostatic discharge protection circuit device and a manufacturing method for the same | Jun 26, 2002 | Issued |
Array
(
[id] => 1231315
[patent_doc_number] => 06692994
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-17
[patent_title] => 'Method for manufacturing a programmable chalcogenide fuse within a semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/180645
[patent_app_country] => US
[patent_app_date] => 2002-06-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/692/06692994.pdf
[firstpage_image] =>[orig_patent_app_number] => 10180645
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/180645 | Method for manufacturing a programmable chalcogenide fuse within a semiconductor device | Jun 25, 2002 | Issued |
Array
(
[id] => 1216376
[patent_doc_number] => 06706570
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-16
[patent_title] => 'Laser illumination system'
[patent_app_type] => B2
[patent_app_number] => 10/178349
[patent_app_country] => US
[patent_app_date] => 2002-06-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/706/06706570.pdf
[firstpage_image] =>[orig_patent_app_number] => 10178349
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/178349 | Laser illumination system | Jun 24, 2002 | Issued |
Array
(
[id] => 1163155
[patent_doc_number] => 06759298
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-06
[patent_title] => 'Methods of forming an array of flash field effect transistors and circuitry peripheral to such array'
[patent_app_type] => B2
[patent_app_number] => 10/179868
[patent_app_country] => US
[patent_app_date] => 2002-06-24
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/759/06759298.pdf
[firstpage_image] =>[orig_patent_app_number] => 10179868
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/179868 | Methods of forming an array of flash field effect transistors and circuitry peripheral to such array | Jun 23, 2002 | Issued |
Array
(
[id] => 6651080
[patent_doc_number] => 20030008418
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-09
[patent_title] => 'Methods of microstructuring ferroelectric materials'
[patent_app_type] => new
[patent_app_number] => 10/170338
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10170338
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/170338 | Methods of microstructuring ferroelectric materials | Jun 13, 2002 | Issued |
Array
(
[id] => 1318178
[patent_doc_number] => 06605489
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-12
[patent_title] => 'Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice'
[patent_app_type] => B2
[patent_app_number] => 10/156976
[patent_app_country] => US
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[pdf_file] => patents/06/605/06605489.pdf
[firstpage_image] =>[orig_patent_app_number] => 10156976
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/156976 | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice | May 28, 2002 | Issued |
Array
(
[id] => 1299911
[patent_doc_number] => 06624089
[patent_country] => US
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[patent_issue_date] => 2003-09-23
[patent_title] => 'Wafer planarization using a uniform layer of material and method and apparatus for forming uniform layer of material used in semiconductor processing'
[patent_app_type] => B2
[patent_app_number] => 10/157628
[patent_app_country] => US
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[pdf_file] => patents/06/624/06624089.pdf
[firstpage_image] =>[orig_patent_app_number] => 10157628
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/157628 | Wafer planarization using a uniform layer of material and method and apparatus for forming uniform layer of material used in semiconductor processing | May 27, 2002 | Issued |
Array
(
[id] => 6821835
[patent_doc_number] => 20030219996
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-27
[patent_title] => 'Method of forming a sealing layer on a copper pattern'
[patent_app_type] => new
[patent_app_number] => 10/155718
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[firstpage_image] =>[orig_patent_app_number] => 10155718
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/155718 | Method of forming a sealing layer on a copper pattern | May 23, 2002 | Abandoned |
Array
(
[id] => 1306257
[patent_doc_number] => 06621165
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-16
[patent_title] => 'Semiconductor device fabricated by reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface'
[patent_app_type] => B1
[patent_app_number] => 10/154871
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/621/06621165.pdf
[firstpage_image] =>[orig_patent_app_number] => 10154871
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/154871 | Semiconductor device fabricated by reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface | May 22, 2002 | Issued |
Array
(
[id] => 1394012
[patent_doc_number] => 06541336
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-01
[patent_title] => 'Method of fabricating a bipolar transistor having a realigned emitter'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/147248 | Method of fabricating a bipolar transistor having a realigned emitter | May 14, 2002 | Issued |
Array
(
[id] => 1303071
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[patent_issue_date] => 2003-09-16
[patent_title] => 'Low resistivity deep trench fill for DRAM and EDRAM applications'
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[firstpage_image] =>[orig_patent_app_number] => 10142518
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/142518 | Low resistivity deep trench fill for DRAM and EDRAM applications | May 8, 2002 | Issued |
Array
(
[id] => 1056831
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[patent_country] => US
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[patent_issue_date] => 2005-02-15
[patent_title] => 'Memory device with a self-assembled polymer film and method of making the same'
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[firstpage_image] =>[orig_patent_app_number] => 10139745
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/139745 | Memory device with a self-assembled polymer film and method of making the same | May 6, 2002 | Issued |
Array
(
[id] => 1393778
[patent_doc_number] => 06541325
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-04-01
[patent_title] => 'Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby'
[patent_app_type] => B2
[patent_app_number] => 10/136118
[patent_app_country] => US
[patent_app_date] => 2002-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/06/541/06541325.pdf
[firstpage_image] =>[orig_patent_app_number] => 10136118
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/136118 | Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby | Apr 30, 2002 | Issued |