Mikado Ryan Buiz
Examiner (ID: 12419, Phone: (571)272-6578 , Office: P/3600 )
Most Active Art Unit | 3506 |
Art Unit(s) | 3731, 2899, 3506 |
Total Applications | 2305 |
Issued Applications | 2195 |
Pending Applications | 18 |
Abandoned Applications | 92 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1327177
[patent_doc_number] => 06599817
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-29
[patent_title] => 'Semiconductor constructions, and methods of forming semiconductor constructions'
[patent_app_type] => B1
[patent_app_number] => 10/133168
[patent_app_country] => US
[patent_app_date] => 2002-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 6250
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/599/06599817.pdf
[firstpage_image] =>[orig_patent_app_number] => 10133168
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/133168 | Semiconductor constructions, and methods of forming semiconductor constructions | Apr 25, 2002 | Issued |
Array
(
[id] => 1149565
[patent_doc_number] => 06770557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-03
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => B2
[patent_app_number] => 10/131478
[patent_app_country] => US
[patent_app_date] => 2002-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 1781
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/770/06770557.pdf
[firstpage_image] =>[orig_patent_app_number] => 10131478
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/131478 | Semiconductor device and method of fabricating the same | Apr 24, 2002 | Issued |
Array
(
[id] => 1341335
[patent_doc_number] => 06586300
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-01
[patent_title] => 'Spacer assisted trench top isolation for vertical DRAM\'s'
[patent_app_type] => B1
[patent_app_number] => 10/125118
[patent_app_country] => US
[patent_app_date] => 2002-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3790
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/586/06586300.pdf
[firstpage_image] =>[orig_patent_app_number] => 10125118
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/125118 | Spacer assisted trench top isolation for vertical DRAM's | Apr 17, 2002 | Issued |
Array
(
[id] => 1416302
[patent_doc_number] => 06518167
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Method of forming a metal or metal nitride interface layer between silicon nitride and copper'
[patent_app_type] => B1
[patent_app_number] => 10/123588
[patent_app_country] => US
[patent_app_date] => 2002-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2147
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/518/06518167.pdf
[firstpage_image] =>[orig_patent_app_number] => 10123588
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/123588 | Method of forming a metal or metal nitride interface layer between silicon nitride and copper | Apr 15, 2002 | Issued |
Array
(
[id] => 6787793
[patent_doc_number] => 20030139032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-24
[patent_title] => 'Metal post manufacturing method'
[patent_app_type] => new
[patent_app_number] => 10/124068
[patent_app_country] => US
[patent_app_date] => 2002-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5731
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0139/20030139032.pdf
[firstpage_image] =>[orig_patent_app_number] => 10124068
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/124068 | Metal post manufacturing method | Apr 14, 2002 | Issued |
Array
(
[id] => 1132324
[patent_doc_number] => 06787844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-07
[patent_title] => 'Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same'
[patent_app_type] => B2
[patent_app_number] => 10/118039
[patent_app_country] => US
[patent_app_date] => 2002-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 4799
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/787/06787844.pdf
[firstpage_image] =>[orig_patent_app_number] => 10118039
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/118039 | Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same | Apr 8, 2002 | Issued |
Array
(
[id] => 1172322
[patent_doc_number] => 06750066
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-15
[patent_title] => 'Precision high-K intergate dielectric layer'
[patent_app_type] => B1
[patent_app_number] => 10/117818
[patent_app_country] => US
[patent_app_date] => 2002-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 0
[patent_no_of_words] => 6859
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/750/06750066.pdf
[firstpage_image] =>[orig_patent_app_number] => 10117818
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/117818 | Precision high-K intergate dielectric layer | Apr 7, 2002 | Issued |
Array
(
[id] => 1220553
[patent_doc_number] => 06703300
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-09
[patent_title] => 'Method for making multilayer electronic devices'
[patent_app_type] => B2
[patent_app_number] => 10/112088
[patent_app_country] => US
[patent_app_date] => 2002-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2074
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/703/06703300.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112088
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112088 | Method for making multilayer electronic devices | Mar 28, 2002 | Issued |
Array
(
[id] => 6674432
[patent_doc_number] => 20030060035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-27
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/106198
[patent_app_country] => US
[patent_app_date] => 2002-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2869
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20030060035.pdf
[firstpage_image] =>[orig_patent_app_number] => 10106198
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/106198 | Semiconductor device | Mar 26, 2002 | Issued |
Array
(
[id] => 1165037
[patent_doc_number] => 06756246
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-29
[patent_title] => 'Method for fabricating III-V group compound semiconductor'
[patent_app_type] => B2
[patent_app_number] => 10/105238
[patent_app_country] => US
[patent_app_date] => 2002-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 5973
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/756/06756246.pdf
[firstpage_image] =>[orig_patent_app_number] => 10105238
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/105238 | Method for fabricating III-V group compound semiconductor | Mar 25, 2002 | Issued |
Array
(
[id] => 5844465
[patent_doc_number] => 20020132376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-19
[patent_title] => 'Fluorescence-enhanced chip'
[patent_app_type] => new
[patent_app_number] => 10/090518
[patent_app_country] => US
[patent_app_date] => 2002-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1257
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0132/20020132376.pdf
[firstpage_image] =>[orig_patent_app_number] => 10090518
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/090518 | Fluorescence-enhanced chip | Mar 3, 2002 | Issued |
Array
(
[id] => 1231337
[patent_doc_number] => 06693004
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-17
[patent_title] => 'Interfacial barrier layer in semiconductor devices with high-K gate dielectric material'
[patent_app_type] => B1
[patent_app_number] => 10/085318
[patent_app_country] => US
[patent_app_date] => 2002-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5849
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/693/06693004.pdf
[firstpage_image] =>[orig_patent_app_number] => 10085318
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/085318 | Interfacial barrier layer in semiconductor devices with high-K gate dielectric material | Feb 26, 2002 | Issued |
Array
(
[id] => 1274151
[patent_doc_number] => 06649535
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-18
[patent_title] => 'Method for ultra-thin gate oxide growth'
[patent_app_type] => B1
[patent_app_number] => 10/074928
[patent_app_country] => US
[patent_app_date] => 2002-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2057
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/649/06649535.pdf
[firstpage_image] =>[orig_patent_app_number] => 10074928
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/074928 | Method for ultra-thin gate oxide growth | Feb 11, 2002 | Issued |
Array
(
[id] => 6755918
[patent_doc_number] => 20030003695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-02
[patent_title] => 'Semiconductor substrate, SOI substrate and manufacturing method therefor'
[patent_app_type] => new
[patent_app_number] => 10/068988
[patent_app_country] => US
[patent_app_date] => 2002-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4950
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20030003695.pdf
[firstpage_image] =>[orig_patent_app_number] => 10068988
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/068988 | Semiconductor substrate, SOI substrate and manufacturing method therefor | Feb 10, 2002 | Issued |
Array
(
[id] => 6843243
[patent_doc_number] => 20030148590
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-07
[patent_title] => 'Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack'
[patent_app_type] => new
[patent_app_number] => 10/066668
[patent_app_country] => US
[patent_app_date] => 2002-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3908
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20030148590.pdf
[firstpage_image] =>[orig_patent_app_number] => 10066668
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/066668 | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack | Feb 5, 2002 | Issued |
Array
(
[id] => 1332599
[patent_doc_number] => 06596636
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-22
[patent_title] => 'ALD method to improve surface coverage'
[patent_app_type] => B2
[patent_app_number] => 10/059308
[patent_app_country] => US
[patent_app_date] => 2002-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 3917
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/596/06596636.pdf
[firstpage_image] =>[orig_patent_app_number] => 10059308
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/059308 | ALD method to improve surface coverage | Jan 30, 2002 | Issued |
Array
(
[id] => 6157992
[patent_doc_number] => 20020146855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-10
[patent_title] => 'Nitride-based semiconductor laser device and method of forming the same'
[patent_app_type] => new
[patent_app_number] => 10/058378
[patent_app_country] => US
[patent_app_date] => 2002-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 18777
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20020146855.pdf
[firstpage_image] =>[orig_patent_app_number] => 10058378
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/058378 | Nitride-based semiconductor laser device and method of forming the same | Jan 29, 2002 | Issued |
Array
(
[id] => 1264490
[patent_doc_number] => 06660619
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-09
[patent_title] => 'Dual damascene metal interconnect structure with dielectric studs'
[patent_app_type] => B1
[patent_app_number] => 10/058048
[patent_app_country] => US
[patent_app_date] => 2002-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2965
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/660/06660619.pdf
[firstpage_image] =>[orig_patent_app_number] => 10058048
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/058048 | Dual damascene metal interconnect structure with dielectric studs | Jan 28, 2002 | Issued |
Array
(
[id] => 6618103
[patent_doc_number] => 20020064904
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-30
[patent_title] => 'Connecting method of semiconductor element and semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/056018
[patent_app_country] => US
[patent_app_date] => 2002-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4490
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20020064904.pdf
[firstpage_image] =>[orig_patent_app_number] => 10056018
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/056018 | Connecting method of semiconductor element and semiconductor device | Jan 27, 2002 | Abandoned |
Array
(
[id] => 6851572
[patent_doc_number] => 20030143775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-31
[patent_title] => 'Wafer-level through-wafer packaging process for mems and mems package produced thereby'
[patent_app_type] => new
[patent_app_number] => 10/057368
[patent_app_country] => US
[patent_app_date] => 2002-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3316
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0143/20030143775.pdf
[firstpage_image] =>[orig_patent_app_number] => 10057368
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/057368 | Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby | Jan 24, 2002 | Issued |