Search

Milton I. Cano

Supervisory Patent Examiner (ID: 14960, Phone: (571)272-1398 , Office: P/1723 )

Most Active Art Unit
1761
Art Unit(s)
1809, 1302, 1761, 1723, 1754, 1763, 1796, 1794, 2899
Total Applications
758
Issued Applications
479
Pending Applications
80
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4253200 [patent_doc_number] => 06137144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'On-chip ESD protection in dual voltage CMOS' [patent_app_type] => 1 [patent_app_number] => 9/281189 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 2907 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137144.pdf [firstpage_image] =>[orig_patent_app_number] => 281189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/281189
On-chip ESD protection in dual voltage CMOS Mar 29, 1999 Issued
Array ( [id] => 4197385 [patent_doc_number] => 06043529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Semiconductor configuration with a protected barrier for a stacked cell' [patent_app_type] => 1 [patent_app_number] => 9/282099 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2760 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043529.pdf [firstpage_image] =>[orig_patent_app_number] => 282099 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282099
Semiconductor configuration with a protected barrier for a stacked cell Mar 29, 1999 Issued
Array ( [id] => 4108273 [patent_doc_number] => 06100560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Nonvolatile cell' [patent_app_type] => 1 [patent_app_number] => 9/277616 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3228 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100560.pdf [firstpage_image] =>[orig_patent_app_number] => 277616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277616
Nonvolatile cell Mar 25, 1999 Issued
Array ( [id] => 4102998 [patent_doc_number] => 06049107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Sub-quarter-micron MOSFET and method of its manufacturing' [patent_app_type] => 1 [patent_app_number] => 9/277558 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2285 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049107.pdf [firstpage_image] =>[orig_patent_app_number] => 277558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277558
Sub-quarter-micron MOSFET and method of its manufacturing Mar 25, 1999 Issued
Array ( [id] => 4123441 [patent_doc_number] => 06072215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Semiconductor device including lateral MOS element' [patent_app_type] => 1 [patent_app_number] => 9/275868 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 6879 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072215.pdf [firstpage_image] =>[orig_patent_app_number] => 275868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275868
Semiconductor device including lateral MOS element Mar 24, 1999 Issued
Array ( [id] => 4101878 [patent_doc_number] => 06097078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method for forming triple well in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/275908 [patent_app_country] => US [patent_app_date] => 1999-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4212 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097078.pdf [firstpage_image] =>[orig_patent_app_number] => 275908 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275908
Method for forming triple well in semiconductor device Mar 23, 1999 Issued
Array ( [id] => 4362763 [patent_doc_number] => 06175148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Electrical connection for a power semiconductor component' [patent_app_type] => 1 [patent_app_number] => 9/272669 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2425 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175148.pdf [firstpage_image] =>[orig_patent_app_number] => 272669 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/272669
Electrical connection for a power semiconductor component Mar 17, 1999 Issued
Array ( [id] => 4195029 [patent_doc_number] => 06153917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Semiconductor acceleration sensor and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/270659 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 32 [patent_no_of_words] => 2924 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153917.pdf [firstpage_image] =>[orig_patent_app_number] => 270659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270659
Semiconductor acceleration sensor and manufacturing method thereof Mar 15, 1999 Issued
Array ( [id] => 4104955 [patent_doc_number] => 06066867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Current control functional device' [patent_app_type] => 1 [patent_app_number] => 9/272739 [patent_app_country] => US [patent_app_date] => 1999-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 6684 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066867.pdf [firstpage_image] =>[orig_patent_app_number] => 272739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/272739
Current control functional device Mar 7, 1999 Issued
Array ( [id] => 4179794 [patent_doc_number] => 06084277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Lateral power MOSFET with improved gate design' [patent_app_type] => 1 [patent_app_number] => 9/253319 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6438 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084277.pdf [firstpage_image] =>[orig_patent_app_number] => 253319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253319
Lateral power MOSFET with improved gate design Feb 17, 1999 Issued
Array ( [id] => 4132216 [patent_doc_number] => 06127695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Lateral field effect transistor of SiC, a method for production thereof and a use of such a transistor' [patent_app_type] => 1 [patent_app_number] => 9/247469 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 4879 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127695.pdf [firstpage_image] =>[orig_patent_app_number] => 247469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/247469
Lateral field effect transistor of SiC, a method for production thereof and a use of such a transistor Feb 7, 1999 Issued
Array ( [id] => 4168887 [patent_doc_number] => 06140171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication' [patent_app_type] => 1 [patent_app_number] => 9/233549 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2119 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140171.pdf [firstpage_image] =>[orig_patent_app_number] => 233549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233549
FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication Jan 19, 1999 Issued
Array ( [id] => 3947327 [patent_doc_number] => 05981999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Power trench DMOS with large active cell density' [patent_app_type] => 1 [patent_app_number] => 9/226278 [patent_app_country] => US [patent_app_date] => 1999-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2163 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981999.pdf [firstpage_image] =>[orig_patent_app_number] => 226278 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226278
Power trench DMOS with large active cell density Jan 6, 1999 Issued
Array ( [id] => 4145708 [patent_doc_number] => 06060783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Self-aligned contact plugs' [patent_app_type] => 1 [patent_app_number] => 9/225593 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5651 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060783.pdf [firstpage_image] =>[orig_patent_app_number] => 225593 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225593
Self-aligned contact plugs Jan 5, 1999 Issued
Array ( [id] => 4137590 [patent_doc_number] => 06147385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'CMOS static random access memory devices' [patent_app_type] => 1 [patent_app_number] => 9/218819 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7076 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147385.pdf [firstpage_image] =>[orig_patent_app_number] => 218819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/218819
CMOS static random access memory devices Dec 21, 1998 Issued
Array ( [id] => 4179688 [patent_doc_number] => 06084269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Semiconductor device and method of making' [patent_app_type] => 1 [patent_app_number] => 9/218368 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6471 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084269.pdf [firstpage_image] =>[orig_patent_app_number] => 218368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/218368
Semiconductor device and method of making Dec 20, 1998 Issued
Array ( [id] => 4148036 [patent_doc_number] => 06031275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Antifuse with a silicide layer overlying a diffusion region' [patent_app_type] => 1 [patent_app_number] => 9/211618 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031275.pdf [firstpage_image] =>[orig_patent_app_number] => 211618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/211618
Antifuse with a silicide layer overlying a diffusion region Dec 14, 1998 Issued
Array ( [id] => 4180265 [patent_doc_number] => 06084307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Bi-level digit line architecture for high density DRAMS' [patent_app_type] => 1 [patent_app_number] => 9/211662 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3262 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084307.pdf [firstpage_image] =>[orig_patent_app_number] => 211662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/211662
Bi-level digit line architecture for high density DRAMS Dec 14, 1998 Issued
Array ( [id] => 4243863 [patent_doc_number] => 06081011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'CMOS logic gate having buried channel NMOS transistor for semiconductor devices and fabrication method of the same' [patent_app_type] => 1 [patent_app_number] => 9/200458 [patent_app_country] => US [patent_app_date] => 1998-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3184 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081011.pdf [firstpage_image] =>[orig_patent_app_number] => 200458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200458
CMOS logic gate having buried channel NMOS transistor for semiconductor devices and fabrication method of the same Nov 26, 1998 Issued
Array ( [id] => 3944119 [patent_doc_number] => 05973359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'MOS type semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/190929 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5921 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973359.pdf [firstpage_image] =>[orig_patent_app_number] => 190929 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190929
MOS type semiconductor device Nov 11, 1998 Issued
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