
Milton I. Cano
Supervisory Patent Examiner (ID: 14960, Phone: (571)272-1398 , Office: P/1723 )
| Most Active Art Unit | 1761 |
| Art Unit(s) | 1809, 1302, 1761, 1723, 1754, 1763, 1796, 1794, 2899 |
| Total Applications | 758 |
| Issued Applications | 479 |
| Pending Applications | 80 |
| Abandoned Applications | 201 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4253200
[patent_doc_number] => 06137144
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'On-chip ESD protection in dual voltage CMOS'
[patent_app_type] => 1
[patent_app_number] => 9/281189
[patent_app_country] => US
[patent_app_date] => 1999-03-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/137/06137144.pdf
[firstpage_image] =>[orig_patent_app_number] => 281189
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/281189 | On-chip ESD protection in dual voltage CMOS | Mar 29, 1999 | Issued |
Array
(
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[patent_doc_number] => 06043529
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[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Semiconductor configuration with a protected barrier for a stacked cell'
[patent_app_type] => 1
[patent_app_number] => 9/282099
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[patent_app_date] => 1999-03-30
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/282099 | Semiconductor configuration with a protected barrier for a stacked cell | Mar 29, 1999 | Issued |
Array
(
[id] => 4108273
[patent_doc_number] => 06100560
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[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Nonvolatile cell'
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[patent_app_number] => 9/277616
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[patent_app_date] => 1999-03-26
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[firstpage_image] =>[orig_patent_app_number] => 277616
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/277616 | Nonvolatile cell | Mar 25, 1999 | Issued |
Array
(
[id] => 4102998
[patent_doc_number] => 06049107
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[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Sub-quarter-micron MOSFET and method of its manufacturing'
[patent_app_type] => 1
[patent_app_number] => 9/277558
[patent_app_country] => US
[patent_app_date] => 1999-03-26
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 277558
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/277558 | Sub-quarter-micron MOSFET and method of its manufacturing | Mar 25, 1999 | Issued |
Array
(
[id] => 4123441
[patent_doc_number] => 06072215
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Semiconductor device including lateral MOS element'
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[firstpage_image] =>[orig_patent_app_number] => 275868
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/275868 | Semiconductor device including lateral MOS element | Mar 24, 1999 | Issued |
Array
(
[id] => 4101878
[patent_doc_number] => 06097078
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[patent_issue_date] => 2000-08-01
[patent_title] => 'Method for forming triple well in semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/275908
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[firstpage_image] =>[orig_patent_app_number] => 275908
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/275908 | Method for forming triple well in semiconductor device | Mar 23, 1999 | Issued |
Array
(
[id] => 4362763
[patent_doc_number] => 06175148
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[patent_kind] => NA
[patent_issue_date] => 2001-01-16
[patent_title] => 'Electrical connection for a power semiconductor component'
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[patent_app_number] => 9/272669
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[pdf_file] => patents/06/175/06175148.pdf
[firstpage_image] =>[orig_patent_app_number] => 272669
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/272669 | Electrical connection for a power semiconductor component | Mar 17, 1999 | Issued |
Array
(
[id] => 4195029
[patent_doc_number] => 06153917
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[patent_issue_date] => 2000-11-28
[patent_title] => 'Semiconductor acceleration sensor and manufacturing method thereof'
[patent_app_type] => 1
[patent_app_number] => 9/270659
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[pdf_file] => patents/06/153/06153917.pdf
[firstpage_image] =>[orig_patent_app_number] => 270659
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/270659 | Semiconductor acceleration sensor and manufacturing method thereof | Mar 15, 1999 | Issued |
Array
(
[id] => 4104955
[patent_doc_number] => 06066867
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[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Current control functional device'
[patent_app_type] => 1
[patent_app_number] => 9/272739
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/272739 | Current control functional device | Mar 7, 1999 | Issued |
Array
(
[id] => 4179794
[patent_doc_number] => 06084277
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[patent_issue_date] => 2000-07-04
[patent_title] => 'Lateral power MOSFET with improved gate design'
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[patent_app_number] => 9/253319
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[firstpage_image] =>[orig_patent_app_number] => 253319
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Array
(
[id] => 4132216
[patent_doc_number] => 06127695
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[patent_issue_date] => 2000-10-03
[patent_title] => 'Lateral field effect transistor of SiC, a method for production thereof and a use of such a transistor'
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Array
(
[id] => 4168887
[patent_doc_number] => 06140171
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[patent_issue_date] => 2000-10-31
[patent_title] => 'FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication'
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Array
(
[id] => 3947327
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[patent_title] => 'Power trench DMOS with large active cell density'
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Array
(
[id] => 4145708
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[patent_title] => 'Self-aligned contact plugs'
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Array
(
[id] => 4137590
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[patent_issue_date] => 2000-11-14
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Array
(
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Array
(
[id] => 4148036
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[patent_issue_date] => 2000-02-29
[patent_title] => 'Antifuse with a silicide layer overlying a diffusion region'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/211618 | Antifuse with a silicide layer overlying a diffusion region | Dec 14, 1998 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/211662 | Bi-level digit line architecture for high density DRAMS | Dec 14, 1998 | Issued |
Array
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Array
(
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[pdf_file] => patents/05/973/05973359.pdf
[firstpage_image] =>[orig_patent_app_number] => 190929
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/190929 | MOS type semiconductor device | Nov 11, 1998 | Issued |