Search

Mimosa De

Examiner (ID: 12073, Phone: (571)272-2637 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2913, 2900, 5332, 2931
Total Applications
6543
Issued Applications
6483
Pending Applications
22
Abandoned Applications
45

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19819137 [patent_doc_number] => 20250077344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => FLASH MEMORY CONTROLLER, OPERATING METHOD OF FLASH MEMORY CONTROLLER, AND STORAGE DEVICE CAPABLE OF PERFORMING DIFFERENT DIMENSION ERROR CORRECTION TO PROTECT DATA [patent_app_type] => utility [patent_app_number] => 18/810493 [patent_app_country] => US [patent_app_date] => 2024-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/810493
FLASH MEMORY CONTROLLER, OPERATING METHOD OF FLASH MEMORY CONTROLLER, AND STORAGE DEVICE CAPABLE OF PERFORMING DIFFERENT DIMENSION ERROR CORRECTION TO PROTECT DATA Aug 19, 2024 Pending
Array ( [id] => 20251766 [patent_doc_number] => 20250300635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => Hybrid Scan Chains with Flip-flops and Latches [patent_app_type] => utility [patent_app_number] => 18/752645 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752645
Hybrid Scan Chains with Flip-flops and Latches Jun 23, 2024 Pending
Array ( [id] => 20427682 [patent_doc_number] => 20250389772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => SIGNAL SEPARATION DEVICE AND SIGNAL SEPARATION METHOD [patent_app_type] => utility [patent_app_number] => 18/747513 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747513
SIGNAL SEPARATION DEVICE AND SIGNAL SEPARATION METHOD Jun 18, 2024 Pending
Array ( [id] => 19469282 [patent_doc_number] => 20240322952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PACKET LOSS MANAGEMENT METHOD AND RELATED APPARATUS [patent_app_type] => utility [patent_app_number] => 18/674011 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674011 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674011
PACKET LOSS MANAGEMENT METHOD AND RELATED APPARATUS May 23, 2024 Pending
Array ( [id] => 19819725 [patent_doc_number] => 20250077932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => Managing Noise Mitigation for Quantum Networks [patent_app_type] => utility [patent_app_number] => 18/650857 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 44030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -104 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650857
Managing Noise Mitigation for Quantum Networks Apr 29, 2024 Pending
Array ( [id] => 20298510 [patent_doc_number] => 20250323753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => POLAR CODING WITH EFFICIENT POLARIZATION [patent_app_type] => utility [patent_app_number] => 18/631995 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631995 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631995
POLAR CODING WITH EFFICIENT POLARIZATION Apr 9, 2024 Pending
Array ( [id] => 19335361 [patent_doc_number] => 20240249791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES [patent_app_type] => utility [patent_app_number] => 18/624070 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624070
Multiple test modes for a memory in an integrated circuit Mar 31, 2024 Issued
Array ( [id] => 19307144 [patent_doc_number] => 20240235724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => COMMUNICATION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/614675 [patent_app_country] => US [patent_app_date] => 2024-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614675 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614675
COMMUNICATION METHOD AND APPARATUS Mar 23, 2024 Pending
Array ( [id] => 19433934 [patent_doc_number] => 20240302432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => BUILT-IN SELF TEST CIRCUIT FOR MEASURING PERFORMANCE OF CLOCK DATA RECOVERY AND SYSTEM-ON-CHIP INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/597499 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597499
Built-in self test circuit for measuring performance of clock data recovery and system-on-chip including the same Mar 5, 2024 Issued
Array ( [id] => 20389118 [patent_doc_number] => 12488851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Content addressable memory apparatus, content addressable memory circuit and memory self-test method thereof [patent_app_type] => utility [patent_app_number] => 18/595469 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595469
Content addressable memory apparatus, content addressable memory circuit and memory self-test method thereof Mar 4, 2024 Issued
Array ( [id] => 20208130 [patent_doc_number] => 20250277850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => ENHANCED DESIGN FOR TEST ARCHITECTURE TO POWER COLLAPSE DESIGN FOR TEST LOGIC [patent_app_type] => utility [patent_app_number] => 18/591540 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591540 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591540
ENHANCED DESIGN FOR TEST ARCHITECTURE TO POWER COLLAPSE DESIGN FOR TEST LOGIC Feb 28, 2024 Pending
Array ( [id] => 19406167 [patent_doc_number] => 20240289678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SYSTEM AND METHODS FOR QUANTUM POST-SELECTION USING LOGICAL SYNDROME COMPRESSION [patent_app_type] => utility [patent_app_number] => 18/590809 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590809 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590809
SYSTEM AND METHODS FOR QUANTUM POST-SELECTION USING LOGICAL SYNDROME COMPRESSION Feb 27, 2024 Pending
Array ( [id] => 20389817 [patent_doc_number] => 12489558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Efficient signaling for MU-MIMO enhanced receivers [patent_app_type] => utility [patent_app_number] => 18/585811 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10855 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 416 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18585811 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/585811
Efficient signaling for MU-MIMO enhanced receivers Feb 22, 2024 Issued
Array ( [id] => 19322207 [patent_doc_number] => 20240243755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => Data Validation and Correction using Hybrid Parity and Error Correcting Codes [patent_app_type] => utility [patent_app_number] => 18/397923 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397923 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397923
Data Validation and Correction using Hybrid Parity and Error Correcting Codes Dec 26, 2023 Pending
Array ( [id] => 19250268 [patent_doc_number] => 20240201257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => AUTOMATED TEST PATTERN GENERATION FOR TESTING DESIGN REDACTING RECONFIGURABLE HARDWARE [patent_app_type] => utility [patent_app_number] => 18/536973 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536973 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536973
AUTOMATED TEST PATTERN GENERATION FOR TESTING DESIGN REDACTING RECONFIGURABLE HARDWARE Dec 11, 2023 Pending
Array ( [id] => 19207037 [patent_doc_number] => 20240178936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SOFT TRELLIS DE-SHAPER FOR CONSTELLATION SHAPING [patent_app_type] => utility [patent_app_number] => 18/517169 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18517169 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/517169
SOFT TRELLIS DE-SHAPER FOR CONSTELLATION SHAPING Nov 21, 2023 Pending
Array ( [id] => 19220409 [patent_doc_number] => 20240185113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => FAULT-TOLERANT QUANTUM COMPUTATION [patent_app_type] => utility [patent_app_number] => 18/512860 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512860
FAULT-TOLERANT QUANTUM COMPUTATION Nov 16, 2023 Pending
Array ( [id] => 19851575 [patent_doc_number] => 20250096926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => OUTER CODING HEADER FOR RAN-BASED NETWORK CODING [patent_app_type] => utility [patent_app_number] => 18/513434 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513434 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513434
OUTER CODING HEADER FOR RAN-BASED NETWORK CODING Nov 16, 2023 Pending
Array ( [id] => 19177036 [patent_doc_number] => 20240163010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => OPERATION METHOD FOR AN ELECTRONIC DEVICE AND AN ELECTRONIC DEVICE CAPABLE OF PERFORMING AN ADVANCED LINE CODING [patent_app_type] => utility [patent_app_number] => 18/504650 [patent_app_country] => US [patent_app_date] => 2023-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504650 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/504650
Operation method for an electronic device and an electronic device capable of performing an advanced line coding Nov 7, 2023 Issued
Array ( [id] => 19117235 [patent_doc_number] => 20240128985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => DECODING DEVICE AND DECODING METHOD USING LOW-DENSITY PARITY CHECK CODE INCLUDING CODE DIFFERENT FROM SINGLE PARITY CHECK CODE [patent_app_type] => utility [patent_app_number] => 18/242834 [patent_app_country] => US [patent_app_date] => 2023-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242834 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/242834
DECODING DEVICE AND DECODING METHOD USING LOW-DENSITY PARITY CHECK CODE INCLUDING CODE DIFFERENT FROM SINGLE PARITY CHECK CODE Sep 5, 2023 Pending
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