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Min Huang

Examiner (ID: 15733, Phone: (571)270-5798 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1007
Issued Applications
880
Pending Applications
58
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20196576 [patent_doc_number] => 20250273286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 19/007058 [patent_app_country] => US [patent_app_date] => 2024-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19007058 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/007058
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME Dec 30, 2024 Pending
Array ( [id] => 19893066 [patent_doc_number] => 20250118378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => DATA ERASURE VERIFICATION FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/984469 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/984469
DATA ERASURE VERIFICATION FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY Dec 16, 2024 Pending
Array ( [id] => 20250876 [patent_doc_number] => 20250299745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => NON-VOLATILE MEMORY AND CONTROLLING METHOD OF NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/982170 [patent_app_country] => US [patent_app_date] => 2024-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/982170
NON-VOLATILE MEMORY AND CONTROLLING METHOD OF NON-VOLATILE MEMORY Dec 15, 2024 Pending
Array ( [id] => 20102884 [patent_doc_number] => 20250232820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/968515 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18968515 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/968515
MEMORY DEVICE Dec 3, 2024 Pending
Array ( [id] => 20036070 [patent_doc_number] => 20250174292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY [patent_app_type] => utility [patent_app_number] => 18/968317 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18968317 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/968317
MEMORY Dec 3, 2024 Pending
Array ( [id] => 20751964 [patent_doc_number] => 20260154192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-04 [patent_title] => IN-MEMORY SEARCHING IN NOR FLASH MEMORY USING EUCLIDEAN (L2) DISTANCE COMPUTING [patent_app_type] => utility [patent_app_number] => 18/964183 [patent_app_country] => US [patent_app_date] => 2024-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18964183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/964183
IN-MEMORY SEARCHING IN NOR FLASH MEMORY USING EUCLIDEAN (L2) DISTANCE COMPUTING Nov 28, 2024 Pending
Array ( [id] => 19835503 [patent_doc_number] => 20250087289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => SIGNAL DROP COMPENSATED MEMORY [patent_app_type] => utility [patent_app_number] => 18/960471 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18960471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/960471
SIGNAL DROP COMPENSATED MEMORY Nov 25, 2024 Pending
Array ( [id] => 20027030 [patent_doc_number] => 20250165252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => COMPUTING MACHINE WITH SECURE MATRIX SPACE OF ROW AND COLUMN MAJOR ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/952950 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/952950
COMPUTING MACHINE WITH SECURE MATRIX SPACE OF ROW AND COLUMN MAJOR ACCESS MEMORY Nov 18, 2024 Pending
Array ( [id] => 19820676 [patent_doc_number] => 20250078883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE [patent_app_type] => utility [patent_app_number] => 18/951392 [patent_app_country] => US [patent_app_date] => 2024-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18951392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/951392
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE Nov 17, 2024 Pending
Array ( [id] => 19803734 [patent_doc_number] => 20250069659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => MEMORY CIRCUITS AND DEVICES, AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/949444 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18949444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/949444
MEMORY CIRCUITS AND DEVICES, AND METHODS THEREOF Nov 14, 2024 Pending
Array ( [id] => 20209414 [patent_doc_number] => 20250279134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => WRITE CLOCK BIAS GENERATOR CONFIGURED TO COMPENSATE FOR CHANGE OF THRESHOLD VOLTAGE OF TRANSISTOR ACCORDING TO CHANGE OF TEMPERATURE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/946420 [patent_app_country] => US [patent_app_date] => 2024-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18946420 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/946420
WRITE CLOCK BIAS GENERATOR CONFIGURED TO COMPENSATE FOR CHANGE OF THRESHOLD VOLTAGE OF TRANSISTOR ACCORDING TO CHANGE OF TEMPERATURE AND MEMORY DEVICE INCLUDING THE SAME Nov 12, 2024 Pending
Array ( [id] => 19803756 [patent_doc_number] => 20250069681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => MEMORY [patent_app_type] => utility [patent_app_number] => 18/945588 [patent_app_country] => US [patent_app_date] => 2024-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18945588 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/945588
MEMORY Nov 12, 2024 Pending
Array ( [id] => 20653933 [patent_doc_number] => 20260105957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => WRITING CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/938304 [patent_app_country] => US [patent_app_date] => 2024-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18938304 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/938304
WRITING CIRCUIT Nov 5, 2024 Pending
Array ( [id] => 20010878 [patent_doc_number] => 20250149100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SEMICONDUCTOR NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/938668 [patent_app_country] => US [patent_app_date] => 2024-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18938668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/938668
SEMICONDUCTOR NONVOLATILE MEMORY DEVICE Nov 5, 2024 Pending
Array ( [id] => 20291070 [patent_doc_number] => 20250316313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/934383 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18934383 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/934383
MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE Oct 31, 2024 Pending
Array ( [id] => 20681923 [patent_doc_number] => 20260120748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => MEMORY PHYSICAL LAYER INTERFACE, MEMORY APPARATUS AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/929638 [patent_app_country] => US [patent_app_date] => 2024-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18929638 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/929638
Memory physical layer interface, memory apparatus and method thereof Oct 28, 2024 Issued
Array ( [id] => 20653939 [patent_doc_number] => 20260105963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => WRITING METHOD, READING METHOD AND MEMORY DEVICE FOR HIDING DATA [patent_app_type] => utility [patent_app_number] => 18/914336 [patent_app_country] => US [patent_app_date] => 2024-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18914336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/914336
WRITING METHOD, READING METHOD AND MEMORY DEVICE FOR HIDING DATA Oct 13, 2024 Pending
Array ( [id] => 19865970 [patent_doc_number] => 20250104756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => METHOD AND DEVICE FOR SETTING IO PARAMETERS FOR COMMUNICATION BETWEEN SYSTEM ON CHIP AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/909444 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18909444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/909444
Method and device for setting io parameters for communication between system on chip and memory Oct 7, 2024 Issued
Array ( [id] => 20572065 [patent_doc_number] => 20260065993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => INPUT BUFFER IN MEMORY DEVICES AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/896748 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18896748 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/896748
INPUT BUFFER IN MEMORY DEVICES AND MEMORY SYSTEMS Sep 24, 2024 Pending
Array ( [id] => 19696084 [patent_doc_number] => 20250014629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => METHODS, DEVICES AND SYSTEMS FOR AN IMPROVED MANAGEMENT OF A NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/888626 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18888626 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/888626
METHODS, DEVICES AND SYSTEMS FOR AN IMPROVED MANAGEMENT OF A NON-VOLATILE MEMORY Sep 17, 2024 Pending
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