
Min Huang
Examiner (ID: 3981)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 991 |
| Issued Applications | 867 |
| Pending Applications | 55 |
| Abandoned Applications | 85 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15472901
[patent_doc_number] => 10552328
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => Storage device and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 15/987384
[patent_app_country] => US
[patent_app_date] => 2018-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 13082
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987384
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/987384 | Storage device and operating method thereof | May 22, 2018 | Issued |
Array
(
[id] => 14218351
[patent_doc_number] => 20190121560
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-25
[patent_title] => RECONFIGURABLE MEMORY ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 15/981708
[patent_app_country] => US
[patent_app_date] => 2018-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20727
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981708
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/981708 | Reconfigurable memory architectures | May 15, 2018 | Issued |
Array
(
[id] => 15120819
[patent_doc_number] => 20190347042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-14
[patent_title] => SEMICONDUCTOR DEVICE WITH PSEUDO FLOW THROUGH SCHEME FOR POWER SAVINGS
[patent_app_type] => utility
[patent_app_number] => 15/976724
[patent_app_country] => US
[patent_app_date] => 2018-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4782
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976724
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/976724 | Semiconductor device with pseudo flow through scheme for power savings | May 9, 2018 | Issued |
Array
(
[id] => 17366474
[patent_doc_number] => 11233510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-25
[patent_title] => In memory logic functions using memory arrays
[patent_app_type] => utility
[patent_app_number] => 15/965186
[patent_app_country] => US
[patent_app_date] => 2018-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6799
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15965186
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/965186 | In memory logic functions using memory arrays | Apr 26, 2018 | Issued |
Array
(
[id] => 15400723
[patent_doc_number] => 10541021
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-21
[patent_title] => Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing
[patent_app_type] => utility
[patent_app_number] => 15/958506
[patent_app_country] => US
[patent_app_date] => 2018-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4388
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15958506
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/958506 | Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing | Apr 19, 2018 | Issued |
Array
(
[id] => 15108323
[patent_doc_number] => 10475491
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-12
[patent_title] => Random code generator with antifuse differential cell and associated sensing method
[patent_app_type] => utility
[patent_app_number] => 15/958460
[patent_app_country] => US
[patent_app_date] => 2018-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 8095
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 326
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15958460
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/958460 | Random code generator with antifuse differential cell and associated sensing method | Apr 19, 2018 | Issued |
Array
(
[id] => 15314971
[patent_doc_number] => 10522195
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-31
[patent_title] => Memory system and method for operating the same
[patent_app_type] => utility
[patent_app_number] => 15/958866
[patent_app_country] => US
[patent_app_date] => 2018-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 7724
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15958866
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/958866 | Memory system and method for operating the same | Apr 19, 2018 | Issued |
Array
(
[id] => 15029873
[patent_doc_number] => 20190325941
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => SENSE AMPLIFIER WITH LOWER OFFSET AND INCREASED SPEED
[patent_app_type] => utility
[patent_app_number] => 15/957790
[patent_app_country] => US
[patent_app_date] => 2018-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24960
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15957790
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/957790 | Sense amplifier with lower offset and increased speed | Apr 18, 2018 | Issued |
Array
(
[id] => 14919973
[patent_doc_number] => 10431313
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-01
[patent_title] => Grouping memory cells into sub-blocks for program speed uniformity
[patent_app_type] => utility
[patent_app_number] => 15/923064
[patent_app_country] => US
[patent_app_date] => 2018-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 13203
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15923064
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/923064 | Grouping memory cells into sub-blocks for program speed uniformity | Mar 15, 2018 | Issued |
Array
(
[id] => 15400747
[patent_doc_number] => 10541033
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-21
[patent_title] => Non-volatile memory device and memory system including the same and program method thereof
[patent_app_type] => utility
[patent_app_number] => 15/911208
[patent_app_country] => US
[patent_app_date] => 2018-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 14798
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911208
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/911208 | Non-volatile memory device and memory system including the same and program method thereof | Mar 4, 2018 | Issued |
Array
(
[id] => 17438754
[patent_doc_number] => 11264094
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-01
[patent_title] => Memory cell including multi-level sensing
[patent_app_type] => utility
[patent_app_number] => 15/911350
[patent_app_country] => US
[patent_app_date] => 2018-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 7670
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911350
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/911350 | Memory cell including multi-level sensing | Mar 4, 2018 | Issued |
Array
(
[id] => 12848293
[patent_doc_number] => 20180174604
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => MULTI-LAYER MAGNETOELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/895236
[patent_app_country] => US
[patent_app_date] => 2018-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5674
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -1
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895236
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/895236 | Multi-layer magnetoelectronic device | Feb 12, 2018 | Issued |
Array
(
[id] => 13377941
[patent_doc_number] => 20180240512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-23
[patent_title] => PREDICTING DATA CORRELATION USING MULTIVALUED LOGICAL OUTPUTS IN STATIC RANDOM ACCESS MEMORY (SRAM) STORAGE CELLS
[patent_app_type] => utility
[patent_app_number] => 15/892037
[patent_app_country] => US
[patent_app_date] => 2018-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5989
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15892037
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/892037 | Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells | Feb 7, 2018 | Issued |
Array
(
[id] => 15984249
[patent_doc_number] => 10672459
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Transition coupling circuitry for memory applications
[patent_app_type] => utility
[patent_app_number] => 15/891212
[patent_app_country] => US
[patent_app_date] => 2018-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 11500
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15891212
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/891212 | Transition coupling circuitry for memory applications | Feb 6, 2018 | Issued |
Array
(
[id] => 15199889
[patent_doc_number] => 10497446
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-03
[patent_title] => Memory system controlling data erase for nonvolatile memory and control method for erasing data
[patent_app_type] => utility
[patent_app_number] => 15/890427
[patent_app_country] => US
[patent_app_date] => 2018-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 13690
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890427
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/890427 | Memory system controlling data erase for nonvolatile memory and control method for erasing data | Feb 6, 2018 | Issued |
Array
(
[id] => 15233683
[patent_doc_number] => 10504570
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-10
[patent_title] => Semiconductor device and timing calibration method
[patent_app_type] => utility
[patent_app_number] => 15/889928
[patent_app_country] => US
[patent_app_date] => 2018-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 26
[patent_no_of_words] => 11836
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889928
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/889928 | Semiconductor device and timing calibration method | Feb 5, 2018 | Issued |
Array
(
[id] => 14952585
[patent_doc_number] => 10437557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-08
[patent_title] => Determination of a match between data values stored by several arrays
[patent_app_type] => utility
[patent_app_number] => 15/885316
[patent_app_country] => US
[patent_app_date] => 2018-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 7295
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885316
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/885316 | Determination of a match between data values stored by several arrays | Jan 30, 2018 | Issued |
Array
(
[id] => 12775786
[patent_doc_number] => 20180150430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-31
[patent_title] => INTEGRATED CIRCUIT FOR OPERATING ON A BUS, AND METHOD FOR OPERATING THE INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 15/879854
[patent_app_country] => US
[patent_app_date] => 2018-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3335
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879854
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/879854 | Integrated circuit for operating on a bus, and method for operating the integrated circuit | Jan 24, 2018 | Issued |
Array
(
[id] => 15788651
[patent_doc_number] => 10628049
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-21
[patent_title] => Systems and methods for on-die control of memory command, timing, and/or control signals
[patent_app_type] => utility
[patent_app_number] => 15/870390
[patent_app_country] => US
[patent_app_date] => 2018-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 25583
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870390
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/870390 | Systems and methods for on-die control of memory command, timing, and/or control signals | Jan 11, 2018 | Issued |
Array
(
[id] => 16494040
[patent_doc_number] => 10860080
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-08
[patent_title] => Storage device, semiconductor device, electronic component, and electronic device
[patent_app_type] => utility
[patent_app_number] => 16/476642
[patent_app_country] => US
[patent_app_date] => 2018-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 42
[patent_no_of_words] => 15240
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 344
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476642
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/476642 | Storage device, semiconductor device, electronic component, and electronic device | Jan 8, 2018 | Issued |