
Min Huang
Examiner (ID: 3981)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 991 |
| Issued Applications | 867 |
| Pending Applications | 55 |
| Abandoned Applications | 85 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12712303
[patent_doc_number] => 20180129267
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-10
[patent_title] => MEMORY INTERFACE WITH ADJUSTABLE VOLTAGE AND TERMINATION AND METHODS OF USE
[patent_app_type] => utility
[patent_app_number] => 15/863155
[patent_app_country] => US
[patent_app_date] => 2018-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5347
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863155
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/863155 | Memory interface with adjustable voltage and termination and methods of use | Jan 4, 2018 | Issued |
Array
(
[id] => 14919887
[patent_doc_number] => 10431270
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-01
[patent_title] => Apparatuses for modulating threshold voltages of memory cells
[patent_app_type] => utility
[patent_app_number] => 15/859029
[patent_app_country] => US
[patent_app_date] => 2017-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6588
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859029
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/859029 | Apparatuses for modulating threshold voltages of memory cells | Dec 28, 2017 | Issued |
Array
(
[id] => 14109569
[patent_doc_number] => 20190096460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => MEMORY HOLD MARGIN CHARACTERIZATION AND CORRECTION CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 15/842460
[patent_app_country] => US
[patent_app_date] => 2017-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7198
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842460
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/842460 | Memory hold margin characterization and correction circuit | Dec 13, 2017 | Issued |
Array
(
[id] => 14366457
[patent_doc_number] => 10304540
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-05-28
[patent_title] => Memory device and operation method thereof
[patent_app_type] => utility
[patent_app_number] => 15/841688
[patent_app_country] => US
[patent_app_date] => 2017-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3019
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841688
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/841688 | Memory device and operation method thereof | Dec 13, 2017 | Issued |
Array
(
[id] => 15919623
[patent_doc_number] => 10657051
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-19
[patent_title] => Memory device and operation method thereof
[patent_app_type] => utility
[patent_app_number] => 15/841640
[patent_app_country] => US
[patent_app_date] => 2017-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2735
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841640
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/841640 | Memory device and operation method thereof | Dec 13, 2017 | Issued |
Array
(
[id] => 14397283
[patent_doc_number] => 10311929
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-04
[patent_title] => Resistance change memory
[patent_app_type] => utility
[patent_app_number] => 15/835988
[patent_app_country] => US
[patent_app_date] => 2017-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 40
[patent_no_of_words] => 7073
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835988
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/835988 | Resistance change memory | Dec 7, 2017 | Issued |
Array
(
[id] => 13876049
[patent_doc_number] => 20190034365
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-31
[patent_title] => MEASUREMENT AND OPTIMIZATION OF COMMAND SIGNAL TIMING MARGINS
[patent_app_type] => utility
[patent_app_number] => 15/829524
[patent_app_country] => US
[patent_app_date] => 2017-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16069
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829524
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/829524 | Measurement and optimization of command signal timing margins | Nov 30, 2017 | Issued |
Array
(
[id] => 14768675
[patent_doc_number] => 10395738
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-27
[patent_title] => Operations on memory cells
[patent_app_type] => utility
[patent_app_number] => 15/827119
[patent_app_country] => US
[patent_app_date] => 2017-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 20170
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15827119
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/827119 | Operations on memory cells | Nov 29, 2017 | Issued |
Array
(
[id] => 14381375
[patent_doc_number] => 20190164600
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-30
[patent_title] => COMPARING INPUT DATA TO STORED DATA
[patent_app_type] => utility
[patent_app_number] => 15/827019
[patent_app_country] => US
[patent_app_date] => 2017-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20125
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15827019
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/827019 | Comparing input data to stored data | Nov 29, 2017 | Issued |
Array
(
[id] => 14381369
[patent_doc_number] => 20190164597
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-30
[patent_title] => SYNAPTIC CROSSBAR MEMORY ARRAY
[patent_app_type] => utility
[patent_app_number] => 15/826654
[patent_app_country] => US
[patent_app_date] => 2017-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2958
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826654
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/826654 | Synaptic crossbar memory array | Nov 28, 2017 | Issued |
Array
(
[id] => 16249256
[patent_doc_number] => 10748630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-18
[patent_title] => High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks
[patent_app_type] => utility
[patent_app_number] => 15/826345
[patent_app_country] => US
[patent_app_date] => 2017-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
[patent_figures_cnt] => 51
[patent_no_of_words] => 11188
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 258
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826345
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/826345 | High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks | Nov 28, 2017 | Issued |
Array
(
[id] => 12263542
[patent_doc_number] => 20180082738
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'Signal Processing Circuit'
[patent_app_type] => utility
[patent_app_number] => 15/822850
[patent_app_country] => US
[patent_app_date] => 2017-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10769
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822850
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/822850 | Signal processing circuit | Nov 26, 2017 | Issued |
Array
(
[id] => 16416685
[patent_doc_number] => 10824580
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-03
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/815048
[patent_app_country] => US
[patent_app_date] => 2017-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 10329
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15815048
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/815048 | Semiconductor device | Nov 15, 2017 | Issued |
Array
(
[id] => 14332599
[patent_doc_number] => 10297323
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-21
[patent_title] => Reducing disturbs with delayed ramp up of dummy word line after pre-charge during programming
[patent_app_type] => utility
[patent_app_number] => 15/726686
[patent_app_country] => US
[patent_app_date] => 2017-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 18022
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726686
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/726686 | Reducing disturbs with delayed ramp up of dummy word line after pre-charge during programming | Oct 5, 2017 | Issued |
Array
(
[id] => 14163539
[patent_doc_number] => 20190108872
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-11
[patent_title] => AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT
[patent_app_type] => utility
[patent_app_number] => 15/727448
[patent_app_country] => US
[patent_app_date] => 2017-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19344
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727448
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/727448 | Area efficient write data path circuit for SRAM yield enhancement | Oct 5, 2017 | Issued |
Array
(
[id] => 13216315
[patent_doc_number] => 10122538
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-06
[patent_title] => Antifuse physically unclonable function unit and associated control method
[patent_app_type] => utility
[patent_app_number] => 15/726470
[patent_app_country] => US
[patent_app_date] => 2017-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 5756
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726470
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/726470 | Antifuse physically unclonable function unit and associated control method | Oct 5, 2017 | Issued |
Array
(
[id] => 13666655
[patent_doc_number] => 10163500
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-12-25
[patent_title] => Sense matching for hard and soft memory reads
[patent_app_type] => utility
[patent_app_number] => 15/721774
[patent_app_country] => US
[patent_app_date] => 2017-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 8604
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721774
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/721774 | Sense matching for hard and soft memory reads | Sep 29, 2017 | Issued |
Array
(
[id] => 16692287
[patent_doc_number] => 20210074766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => THREE TERMINAL SELECTORS FOR MEMORY APPLICATIONS AND THEIR METHODS OF FABRICATION
[patent_app_type] => utility
[patent_app_number] => 16/642865
[patent_app_country] => US
[patent_app_date] => 2017-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13212
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16642865
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/642865 | Three terminal selectors for memory applications and their methods of fabrication | Sep 29, 2017 | Issued |
Array
(
[id] => 14555255
[patent_doc_number] => 10346088
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-09
[patent_title] => Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND
[patent_app_type] => utility
[patent_app_number] => 15/721674
[patent_app_country] => US
[patent_app_date] => 2017-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 16896
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721674
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/721674 | Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND | Sep 28, 2017 | Issued |
Array
(
[id] => 16308466
[patent_doc_number] => 10777271
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-15
[patent_title] => Method and apparatus for adjusting demarcation voltages based on cycle count metrics
[patent_app_type] => utility
[patent_app_number] => 15/721438
[patent_app_country] => US
[patent_app_date] => 2017-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 13655
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721438
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/721438 | Method and apparatus for adjusting demarcation voltages based on cycle count metrics | Sep 28, 2017 | Issued |